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4524 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0091-0200Z Rev.2.00 2004.07.27
DESCRIPTION
The 4524 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with main clock selection function, serial I/O, four 8-bit timers (each timer has one or two reload registers), 10-bit A/D converter, interrupts, and LCD control circuit. The various microcomputers in the 4524 Group include variations of the built-in memory size as shown in the table below.
FEATURES
qMinimum instruction execution time .................................. 0.5 s (at 6 MHz oscillation frequency, in high-speed through-mode) qSupply voltage Mask ROM version ...................................................... 2.0 to 5.5 V One Time PROM version ............................................. 2.5 to 5.5 V (It depends on oscillation frequency and operation mode) qTimers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register Timer 3 ...................................... 8-bit timer with a reload register Timer 4 ................................. 8-bit timer with two reload registers Timer 5 .............................. 16-bit timer (fixed dividing frequency) Part number M34524M8-XXXFP M34524MC-XXXFP M34524EDFP (Note)
Note: Shipped in blank.
qInterrupt ........................................................................ 9 sources qKey-on wakeup function pins ................................................... 10 q LCD control circuit Segment output ........................................................................ 20 Common output .......................................................................... 4 qSerial I/O ......................................................................... 8-bit 1 qA/D converter .............. 10-bit successive approximation method qVoltage drop detection circuit (Reset) ......................... Typ. 3.5 V qWatchdog timer qClock generating circuit Main clock (ceramic resonator/RC oscillation/internal on-chip oscillator) Sub-clock (quartz-crystal oscillation) qLED drive directly enabled (port D)
APPLICATION
Household appliance, consumer electronics, office automation equipment
ROM (PROM) size ( 10 bits) 8192 words 12288 words 16384 words
RAM size ( 4 bits) 512 words 512 words 512 words
Package 64P6N-A 64P6N-A 64P6N-A
ROM type Mask ROM Mask ROM One Time PROM
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4524 Group
PIN CONFIGURATION
COM0
COM1
COM2
COM3
P00
P01
P02
P03 P10
P11
P12
P13 D0 D1
D2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VLC3/SEG0 VLC2/SEG1 VLC1/SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D4/SIN D5/SOUT D6/SCK CNVSS VDCE
XCIN XCOUT
VDD VSS XOUT XIN
RESET D7/CNTR0 C/CNTR1
M34524Mx-XXXFP M34524EDFP
D8/INT0 D9/INT1
P33/AIN7 P32/AIN6 P31/AIN5 P30/AIN4 P23/AIN3
OUTLINE 64P6N-A
Pin configuration (top view) (4524 Group)
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P22/AIN2
P21/AIN1
P20/AIN0
SEG17 SEG18 SEG19 P43 P42
SEG16
P41 P40
4524 Group
4 4 4 4 4
Block diagram (4524 Group)
Rev.2.00 Jul 27, 2004 REJ03B0091-0200Z
I/O port
Port P0 Port P1 Port P2 Port P3 Port P4
Internal peripheral functions
System clock generation circuit XIN -XOUT (Main clock) XCIN -XCOUT (Sub-clock) Power-on reset circuit Voltage drop detection circuit
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Timer
Timer 1(8 bits) Timer 2(8 bits) Timer 3(8 bits) Timer 4(8 bits) Timer 5(16 bits)
Watchdog timer (16 bits)
A/D converter (10 bits 8 ch)
Memory
ROM
8192, 12288, 16384 words 10 bits
Serial I/O (8 bits 1)
4500 series CPU core
ALU(4 bits)
Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
LCD drive control circuit (Max.20 segments 4 common)
RAM
512 words 4 bits LCD display RAM including 20 words 4 bits
Segment output 4
Common output
Port C
Port D
20
1
2
8
4524 Group
PERFORMANCE OVERVIEW
Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM M34524M8 M34524MC M34524ED RAM Input/Output D0-D7 I/O ports Function 159 0.5 s (at 6 MHz oscillation frequency, in high-speed through mode) 8192 words 10 bits 12288 words 10 bits 16384 words 10 bits 512 words 4 bits (including LCD display RAM 20 words 4 bits) Eight independent I/O ports. Input is examined by skip decision. The output structure can be switched by software. Ports D4, D5, D6 and D7 are also used as SIN, SOUT, SCK and CNTR0 pin. Two independent output ports. Ports D8 and D9 are also used as INT0 and INT1, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; Ports P20-P23 are also used as AIN0-AIN3, respectively. 4-bit I/O port; Ports P30-P33 are also used as AIN4-AIN7, respectively. 4-bit I/O port; The output structure can be switched by software. 1-bit output; Port C is also used as CNTR1 pin. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with two reload registers. 16-bit timer, fixed dividing frequency 10-bit 1, 8-bit comparator is equipped. 8-bit 1 1/2, 1/3 bias 2, 3, 4 duty 4 20 2r 3, 2r 2, r 3, r 2 (they can be switched by software.) 9 (two for external, five for timer, A/D, serial I/O) 1 level 8 levels CMOS silicon gate 64-pin plastic molded QFP (64P6N) -20 C to 85 C 2 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.) 2.5 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.) 2.8 mA (Ta=25C, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN) = 32 kHz, f(STCK) = f(XIN)) 20 A (Ta=25C, VDD = 5 V, f(XCIN) = 32 kHz) 0.1 A (Ta=25C, VDD = 5 V)
D8, D9
Output
P00-P03 I/O P10-P13 I/O P20-P23 P30-P33 P40-P43 C Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 I/O I/O I/O Output
Timers
A/D converter Serial I/O LCD control Selective bias value circuit Selective duty value Common output Segment output Internal resistor for power supply Interrupt Sources Nesting Subroutine nesting Device structure Package Operating temperature range Supply Mask ROM version voltage One Time PROM version Power Active mode dissipation Clock operating mode At RAM back-up
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4524 Group
PIN DESCRIPTION
Pin VDD VSS CNVSS VDCE Name Power supply Ground CNVSS Voltage drop detection circuit enable Reset input/output Input/Output -- -- -- Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply "L" (0V) to CNVSS certainly. This pin is used to operate/stop the voltage drop detection circuit. When "H" level is input to this pin, the circuit starts operating. When "L" level is input to this pin, the circuit stops operating. An N-channel open-drain I/O pin for a system reset. When the watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs "L" level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. I/O pins of the sub-clock generating circuit. Connect a 32 kHz quartz-crystal oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Ports D4-D7 is also used as SIN, SOUT, SCK and CNTR0 pin. Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. Ports D8 and D9 are also used as INT0 pin and INT1 pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P2 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to "1". Ports P20-P23 are also used as AIN0-AIN3, respectively. Port P3 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to "1". Ports P30-P33 are also used as AIN4-AIN7, respectively. Port P4 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. 1-bit output port. The output structure is CMOS. Port C is also used as CNTR1 pin. LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0- COM2 are used at 1/3 duty and pins COM0-COM3 are used at 1/4 duty. LCD segment output pins. SEG0-SEG2 pins are used as VLC3-VLC1 pins, respectively. LCD power supply pins. When the internal resistor is used, VDD pin is connected to VLC3 pin (if luminance adjustment is required, VDD pin is connected to VLC3 pin through a resistor). When the external power supply is used, apply the voltage 0 VLC1 VLC2 VLC3 VDD. VLC3-VLC1 pins are used as SEG0-SEG2 pins, respectively. CNTR0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to input the clock for the timer 3 event counter, and to output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also used as Ports D7 and C, respectively. INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as Ports D8 and D9, respectively. A/D converter analog input pins. AIN0-AIN7 are also used as ports P20-P23 and P30- P33, respectively. Serial I/O data transfer synchronous clock I/O pin. SCK pin is also used as port D6. Serial I/O data output pin. SOUT pin is also used as port D5. Serial I/O data input pin. SIN pin is also used as port D4.
RESET
I/O
XIN XOUT XCIN XCOUT D0-D7
Main clock input Main clock output Sub-clock input Sub-clock output I/O port D Input is examined by skip decision. Output port D
Input Output Input Output I/O
D8, D9
Output
P00-P03
I/O port P0
I/O
P10-P13
I/O port P1
I/O
P20-P23
I/O port P2
I/O
P30-P33
I/O port P3
I/O
P40-P43
I/O port P4
I/O
Output port C Port C Common output COM0- COM3 SEG0-SEG19 Segment output VLC3-VLC1 LCD power supply
Output Output Output -
CNTR0, CNTR1
Timer input/output
I/O
INT0, INT1
Interrupt input
Input
AIN0-AIN7 SCK SOUT SIN
Analog input Serial I/O data I/O Serial I/O data output Serial I/O clock input
Input I/O Output Input
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4524 Group
MULTIFUNCTION
Pin D4 D5 D6 D7 D8 D9 VLC3 VLC2 VLC1 Multifunction SIN SOUT SCK CNTR0 INT0 INT1 SEG0 SEG1 SEG2 Pin SIN SOUT SCK CNTR0 INT0 INT1 SEG0 SEG1 SEG2 Multifunction D4 D5 D6 D7 D8 D9 VLC3 VLC2 VLC1 Pin C P20 P21 P22 P23 P30 P31 P32 P33 Multifunction CNTR1 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Pin CNTR1 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Multifunction C P20 P21 P22 P23 P30 P31 P32 P33
Notes 1: Pins except above have just single function. 2: The output of D8 and D9 can be used even when INT0 and INT1 are selected. 3: The input of ports D4-D6 can be used even when SIN, SOUT and SCK are selected. 4: The input/output of D7 can be used even when CNTR0 (input) is selected. 5: The input of D7 can be used even when CNTR0 (output) is selected. 6: The port C "H" output function can be used even when CNTR1 (output) is selected.
DEFINITION OF CLOCK AND CYCLE
q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. * Clock (f(XIN)) by the external ceramic resonator * Clock (f(XIN)) by the external RC oscillation * Clock (f(XIN)) by the external input * Clock (f(RING)) of the on-chip oscillator which is the internal oscillator * Clock (f(XCIN)) by the external quartz-crystal oscillation Table Selection of system clock Register MR System clock MR3 MR2 MR1 MR0 0 0 0 0 f(STCK) = f(XIN) or f(RING) 1 f(STCK) = f(XCIN) 0 1 0 0 f(STCK) = f(XIN)/2 or f(RING)/2 1 f(STCK) = f(XCIN)/2 1 0 0 0 f(STCK) = f(XIN)/4 or f(RING)/4 1 f(STCK) = f(XCIN)/4 1 1 0 0 f(STCK) = f(XIN)/8 or f(RING)/8 1 f(STCK) = f(XCIN)/8 : 0 or 1 Note: The f(RING)/8 is selected after system is released from reset.
q System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. q Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction. Operation mode High-speed through mode Low-speed through mode High-speed frequency divided by 2 mode Low-speed frequency divided by 2 mode High-speed frequency divided by 4 mode Low-speed frequency divided by 4 mode High-speed frequency divided by 8 mode Low-speed frequency divided by 8 mode
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PORT FUNCTION
Port Port D Pin D0-D3, D4/SIN, D5/SOUT, D6/SCK, D7/CNTR0 D8/INT0, D9/INT1 Input Output I/O (8) Output (2) I/O (4) I/O (4) I/O (4) I/O (4) I/O (4) Output (1) Output structure N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain N-channel open-drain/ CMOS CMOS 4 OP0A IAP0 OP1A IAP1 OP2A IAP2 OP3A IAP3 OP4A IAP4 RCP SCP I/O unit 1 Control instructions SD, RD SZD CLD Control registers FR1, FR2 J1 W6 I1, I2 K2 FR0 PU0 K0 FR0 PU1 K1 Q2 Q3 FR3 W4 Output structure selection function (programmable) Remark Output structure selection function (programmable) Key-on wakeup function (programmable) Built-in programmable pull-up functions and key-on wakeup functions (programmable) Built-in programmable pull-up functions and key-on wakeup functions (programmable)
Port P0 P00-P03
Port P1 P10-P13
4
Port P2 P20/AIN0-P23/AIN3 Port P3 P30/AIN4-P33/AIN7 Port P4 P40-P43 Port C C/CNTR1
4 4 4 1
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4524 Group
CONNECTIONS OF UNUSED PINS
Pin XIN Connection Connect to VSS. Usage condition Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) Sub-clock input is selected for system clock (MR0=1). (Note 2) Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) RC oscillator is selected (CRCK instruction is executed) External clock input is selected for main clock (CMCK instruction is executed). (Note 3) Sub-clock input is selected for system clock (MR0=1). (Note 2) Sub-clock is not used. Sub-clock is not used. N-channel open-drain is selected for the output structure. (Note 4) SIN pin is not selected. N-channel open-drain is selected for the output structure. N-channel open-drain is selected for the output structure. SCK pin is not selected. N-channel open-drain is selected for the output structure. CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. "0" is set to output latch. "0" is set to output latch. CNTR1 input is not selected for timer 3 count source. The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4)
XOUT
Open.
XCIN XCOUT D0-D3 D4/SIN D5/SOUT D6/SCK D7/CNTR0 D8/INT0 D9/INT1 C/CNTR1 P00-P03
Connect to VSS. Open. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Open. Connect to Vss.
P10-P13
Open. Connect to Vss.
P20/AIN0- P23/AIN3 P30/AIN4- P33/AIN7 P40-P43 COM0-COM3 VLC3/SEG0 VLC2/SEG1 VLC1/SEG2 SEG3-SEG19
Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Open. Open. Open. Open.
N-channel open-drain is selected for the output structure. (Note 5) SEG0 pin is selected. SEG1 pin is selected. SEG2 pin is selected.
Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator) is selected for main clock. 2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting "1" to bit 1 (MR1) of clock control register MR, main clock is stopped. 3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input for the main clock. 4: Be sure to select the output structure of ports D0-D3 and P40-P43 and the pull-up function and key-on wakeup function of P00-P03 and P10-P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00-P03 and P10-P13 with every two ports. If only one of the two pins is used, leave another one open. (Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
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4524 Group
PORT BLOCK DIAGRAMS
Clock (input) for timer 3 event count W31 PWMOD W30 (Note 1) C/CNTR1 (Note 2, Note 3)
SCP instruction RCP instruction
SQ R D Q R T W61
Timer 3 underflow signal
W32
Register Y
Decoder
Skip decision (SZD instruction) FR10 (Note 1) S RQ Skip decision (SZD instruction) FR11 (Note 1) S D1 (Note 2) D0 (Note 2)
CLD instruction SD instruction RD instruction
Register Y
Decoder
CLD instruction SD instruction RD instruction
RQ Skip decision (SZD instruction) FR12 (Note 1) S RQ Skip decision (SZD instruction) FR13 (Note 1) S RQ D3 (Note 2) D2 (Note 2)
Register Y
Decoder
CLD instruction SD instruction RD instruction
Register Y
Decoder
CLD instruction SD instruction RD instruction
This symbol represents a parasitic diode on the port. Notes 1: 2: Applied potential to these ports must be VDD or less. 3: When CNTR1 input is selected, output transistor is turned OFF.
Port block diagram (1)
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4524 Group
Register Y
Decoder
Skip decision (SZD instruction)
CLD instruction SD instruction RD instruction
FR20 (Note 1) SQ R J11 Serial data input Skip decision (SZD instruction) FR21 S J10 RQ
0 1
D4/SIN
(Note 2)
Register Y
Decoder
CLD instruction SD instruction RD instruction Serial data output
(Note 1) D5/SOUT (Note 2)
Register Y
Decoder
Skip decision (SZD instruction)
CLD instruction SD instruction RD instruction J11 J10 Synchronous clock (output) for serial data transfer Synchronous clock (input) for serial data transfer R
FR22 (Note 1) SQ D6/SCK (Note 2)
J13 J12
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less.
Port block diagram (2)
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4524 Group
Register Y
Decoder
Skip decision (SZD instruction) FR23 S W60 RQ
0 1
CLD instruction SD instruction RD instruction
(Note 1) D7/CNTR0 (Note 2)
Underflow signal divided by 2 of timer 1 or timer 2 Clock (input) for timer 1 event count Timer 1 count start synchronous circuit input Key-on wakeup External 0 interrupt Register Y Decoder CLD instruction SD instruction RD instruction Timer 3 count start synchronous circuit input Key-on wakeup External 1 interrupt Register Y Decoder CLD instruction SD instruction RD instruction S RQ S RQ
W11 W10
(Note 3) External 0 interrupt circuit
(Note 1) D8/INT0 (Note 2)
(Note 3) External 1 interrupt circuit
(Note 1) D9/INT1 (Note 2)
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: As for details, refer to the description of external interrupt circuit.
Port block diagram (3)
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4524 Group
IAP0 instruction Register A A0 FR00
Pull-up transistor
PU00
(Note 1) A0 OP0A instruction D TQ K00 Key-on wakeup "L" level detection circuit P00 (Note 2)
IAP0 instruction Register A A1 FR00
Pull-up transistor
PU01
(Note 1) A1 OP0A instruction D TQ K01 Key-on wakeup "L" level detection circuit P01 (Note 2)
Register A A2
IAP0 instruction
Pull-up transistor
PU02
FR01 A2 OP0A instruction D TQ K02 Key-on wakeup "L" level detection circuit (Note 1) P02 (Note 2)
Register A A3
IAP0 instruction
Pull-up transistor
PU03
FR01 A3 OP0A instruction D TQ K03 Key-on wakeup "L" level detection circuit (Note 1) P03 (Note 2)
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less.
Port block diagram (4)
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4524 Group
IAP1 instruction Register A A0 FR02
Pull-up transistor
PU10
(Note 1) A0 OP1A instuction D TQ K10 Key-on wakeup "L" level detection circuit
Pull-up transistor
P10 (Note 2)
IAP1 instruction Register A A1 FR02
PU11
(Note 1) A1 OP1A instuction D TQ K11 Key-on wakeup "L" level detection circuit
Pull-up transistor
P11 (Note 2)
IAP1 instruction Register A A2 FR03
PU12
(Note 1) A2 OP1A instuction D TQ K12 Key-on wakeup "L" level detection circuit
Pull-up transistor
P12 (Note 2)
IAP1 instruction Register A A3 FR03
PU13
(Note 1) A3 OP1A instuction D TQ K13 Key-on wakeup "L" level detection circuit P13 (Note 2)
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less.
Port block diagram (5)
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4524 Group
Ai IAP2 instruction Register A (Note 3) Ai OP2A instruction D TQ (Note 3) Q2i
0 1
Q2i
(Note 3) (Note 1) P20/AIN0-P23/AIN3 (Note 2)
Q1 Decoder Analog input
Ai Register A (Note 3) Ai OP3A instruction D TQ IAP3 instruction Q3i (Note 3) Q3i
0 1
(Note 3) (Note 1) P30/AIN4-P33/AIN7 (Note 2)
Q1 Decoder Analog input
IAP4 instruction Ai Register A (Note 3) Ai OP4A instruction (Note 3) FR3i (Note 1) D TQ P40-P43 (Note 2)
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3.
Port block diagram (6)
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LCD power supply LCD control signal
Connecting to * when SEG is selected.
(Note 1) VLC3/SEG0 (Notes 2 and 3) VDD L23 LCD power supply LCD power supply (VLC3/VDD) LCD power supply LCD control signal
Connecting to * when SEG is selected.
(Note 1) VLC2/SEG1 (Note 2) L22 LCD power supply (VLC2) LCD power supply L11 LCD control signal
Connecting to * when SEG is selected.
LCD power supply
(Note 1) VLC1/SEG2 (Note 2)
L21 LCD power supply LCD power supply (VLC1)
L13 L20 Reset signal L12 EPOF+POF2 instruction (Continuous execution)
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential when VLC is selected must be as follows; * VDD VLC3 VLC2 VLC1 3: VLC3 = VDD when SEG is selected.
Port block diagram (7)
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LCD power supply LCD control signal
Pch
SEG3-SEG19 LCD control signal LCD power supply LCD power supply LCD control signal
Nch
Pch
COM0-COM3
Pch
LCD control signal LCD power supply LCD power supply LCD control signal
Nch
Nch
LCD control signal
Port block diagram (8)
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FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation.
(CY) (M(DP)) Addition (A)
Fig. 1 AMC instruction execution example
ALU
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction.
SC instruction
RC instruction
CY
A3 A2 A1 A0 RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B
TAB instruction
Register A
B3 B2 B1 B0
A3 A2 A1 A0
(4) Register D
Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A
TBA instruction
Fig. 3 Registers A, B and register E
TABP p instruction Specifying address
ROM 8 4 0
PCH p6 p5 p4 p3 p2 p1 p0
PCL DR2DR1DR0 A3 A2 A1 A0
Low-order 4bits Register A (4) Middle-order 4 bits Register B (4)
Immediate field value p
The contents of The contents of register D register A
Fig. 4 TABP p instruction execution example
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4524 Group
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call.
Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7
Stack pointer (SP) points "7" at reset or returning from RAM back-up mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction.
(SP) 0 (SK0) 000116 (PC) SUB1
Main program Address 000016 NOP 000116 BM SUB1 000216 NOP
Subroutine
SUB1 : NOP * * * RT
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.
(PC) (SK0) (SP) 7
Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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4524 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM.
Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH Specifying page
PCL Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers.
Register Y (4)
Specifying RAM digit
Register X (4)
Specifying RAM file
Register Z (2)
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position Set
D3 D2 D1 D0
0
0
0
1
1 Port D output latch
Register Y (4)
Fig. 9 SD instruction execution example
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4524 Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34524ED. Table 1 ROM size and pages Part number M34524M8 M34524MC M34524ED ROM (PROM) size ( 10 bits) 8192 words 12288 words 16384 words Pages 64 (0 to 63) 96 (0 to 95) 128 (0 to 127)
9876543210 000016 007F16 008016 00FF16 010016 017F16 018016 Page 0 Interrupt address page Subroutine special page Page 1 Page 2 Page 3
Note: Data in pages 64 to 127 can be referred with the TABP p instruction after the SBK instruction is executed. Data in pages 0 to 63 can be referred with the TABP p instruction after the RBK instruction is executed. A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
3FFF16
Page 127
Fig. 10 ROM map of M34524ED
008016 008216 008416 008616 008816 008A16 008C16 008E16
9876543210 External 0 interrupt address External 1 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address Timer 5 interrupt address A/D interrupt address
T imer 4, Serial I/O interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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4524 Group
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). RAM includes the area for LCD. When writing "1" to a bit corresponding to displayed segment, the segment is turned on. Table 2 shows the RAM size. Figure 12 shows the RAM map. * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers.
Table 2 RAM size Part number M34524M8 M34524MC M34524ED RAM size 512 words 4 bits (2048 bits) 512 words 4 bits (2048 bits) 512 words 4 bits (2048 bits)
RAM 512 words 4 bits (2048 bits) Register Z 1 0 Register X 0 1 2 3 ... 12 13 14 15 0 1 2 ... 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register Y
12 13 14 15
0 1 2 3 4 5 6
8 16 9 17 10 18 11 19 12 13 14
7 15
Note: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig. 12 RAM map
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4524 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * An interrupt activated condition is satisfied (request flag = "1") * Interrupt enable bit is enabled ("1") * Interrupt enable flag is enabled (INTE = "1") Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.)
Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 3 4 5 6 7 8 External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 5 interrupt A/D interrupt Timer 4 interrupt or Serial I/O interrupt (Note)
Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 5 underflow Completion of A/D conversion Timer 4 underflow or completion of serial I/O transmit/ receive
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed.
Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function.
Note: Timer 4 interrupt or serial I/O interrupt can be selected by the timer 4, serial I/O interrupt source selection bit (I30).
Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 5 interrupt A/D interrupt Timer 4 interrupt Serial I/O interrupt Interrupt request flag EXF0 EXF1 T1F T2F T3F T5F ADF T4F SIOF Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT5 SNZAD SNZT4 SNZSI Interrupt nable bit V10 V11 V12 V13 V20 V21 V22 V23 V23
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * the next instruction is skipped with a skip instruction. Each interrupt request flag is set to "1" when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until it is cleared to "0" by the interrupt occurrence or the skip instruction. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set to "1" when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.
Table 5 Interrupt enable bit function Interrupt enable bit Occurrence of interrupt Enabled 1 Disabled 0
Skip instruction Invalid Valid
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4524 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14). * Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0." * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).
* Program counter (PC) ............................................................... Each interrupt address * Stack register (SK) The address of main routine to be .................................................................................................... executed when returning * Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) * Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 * Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13)
Activated condition INT0 pin interrupt waveform input
Request flag Enable bit (state retained)
Enable flag
EXF0
V10
Address 0 in page 1
INT1 pin interrupt waveform input
EXF1
V11
Address 2 in page 1
Timer 1 underflow
Main routine
Timer 2 underflow
T1F
V12
Address 4 in page 1
Interrupt service routine
Interrupt occurs
T2F
V13
Address 6 in page 1
Timer 3 underflow
T3F
V20
Address 8 in page 1
* * * *
Timer 5 underflow
T5F
V21
Address A in page 1
EI R TI
Interrupt is enabled
A/D conversion completed
ADF
V22
Address C in page 1
Timer 4 underflow
T4F
V23
INTE
Address E in page 1
0 Serial I/O transmit/receive completed 1 SIOF I30
: Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing
Fig. 15 Interrupt system diagram
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4524 Group
(6) Interrupt control registers
* Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. * Interrupt control register V2 The timer 3, timer 5, A/D, Timer 4 and serial I/O interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit 0 1 0 1 0 1 0 1
* Interrupt control register I3 The timer 4, serial I/O interrupt source selection bit is assigned to register I3. Set the contents of this register through register A with the TI3A instruction. The TAI3 instruction can be used to transfer the contents of register I3 to register A.
at reset : 00002
at power down : 00002
R/W TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) (Note 2) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) (Note 2) R/W TAV2/TV2A
Interrupt control register V2 V23 V22 V21 V20 Timer 4, serial I/O interrupt enable bit (Note 3) A/D interrupt enable bit Timer 5 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : 00002
Interrupt disabled (SNZT4, SNZSI instruction is valid) Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 2) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) (Note 2) Interrupt disabled (SNZT5 instruction is valid) Interrupt enabled (SNZT5 instruction is invalid) (Note 2) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) (Note 2) R/W TAI3/TI3A
Interrupt control register I3 I30 Timer 4, serial I/O interrupt source selection bit 0 1
at reset : 02
at power down : state retained
Timer 4 interrupt valid, serial I/O interrupt invalid Serial I/O interrupt valid, timer 4 interrupt invalid
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: These instructions are equivalent to the NOP instruction. 3: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source selection bit (I30).
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10-V13, V20-V23), and interrupt request flag are "1." The interrupt actually occurs 2 to 3 machine cycles after the machine cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles when the interrupt conditions are satisfied on execution of two-cycle instructions or three-cycle instructions. (Refer to Figure 16).
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4524 Group
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T3 T1 T1 T1 T1 T2 T3 T2 T3 T2 T3 T2 Interrupt disabled state Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary. Interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 1, 2) The program starts from the interrupt address.
Fig. 16 Interrupt sequence
q When an interrupt request flag is set after its interrupt is enabled (Note 1)
1 machine cycle
T1
T2
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System clock (STCK)
EI instruction execution cycle
Interrupt enable flag (INTE)
INT0,INT1
External interrupt
EXF0,EXF1
Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, A/D and Serial I/O interrupts
T1F,T2F,T3F,T4F T5F,ADF,SIOF
Notes 1: The address to be executed when returning to the main routine is stacked to the last machine cycle. 2: The cycles are as follows according to the executed instruction at the time when each interrupt activated condition is satisfied. On execution of one-cycle instruction: Interrupt occurs after 2 machine cycles. On execution of two-cycle instruction: Interrupt occurs after 3 machine cycles. On execution of three-cycle instruction: Interrupt occurs after 3 machine cycles.
4524 Group
EXTERNAL INTERRUPTS
The 4524 Group has the external 0 interrupt and external 1 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin D8/INT0 Activated condition When the next waveform is input to D8/INT0 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms External 1 interrupt D9/INT1 When the next waveform is input to D9/INT1 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms I21 I22 Valid waveform selection bit I11 I12
(Note 1) D8/INT0
I12
Falling
0 1
Rising
One-sided edge detection circuit
I11
0
EXF0 Both edges detection circuit (Note 2) Level detection circuit K20 (Note 3) Edge detection circuit
1
External 0 interrupt
I13
Timer 1 count start synchronous circuit K21
0
Key-on wakeup
1
Skip decision (SNZI0 instruction)
I22 (Note 1) D9/INT1
1
Rising Falling
0
One-sided edge detection circuit
I21
0
EXF1 Both edges detection circuit (Note 2) Level detection circuit K22 (Note 3) Edge detection circuit Skip decision (SNZI1 instruction)
1
External 1 interrupt
I23
Timer 3 count start synchronous circuit K23
0
Key-on wakeup
1
Notes 1: This symbol represents a parasitic diode on the port. 2: I12 (I22) = 0: "L" level detected I12 (I22) = 1: "H" level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected
Fig. 17 External interrupt circuit structure
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4524 Group
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to D8/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. * External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D8/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. Set the bit 3 of register I1 to "1" for the INT0 pin to be in the input enabled state. Select the valid waveform with the bits 1 and 2 of register I1. Clear the EXF0 flag to "0" with the SNZ0 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the D8/INT0 pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs.
(2) External 1 interrupt request flag (EXF1)
External 1 interrupt request flag (EXF1) is set to "1" when a valid waveform is input to D9/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. * External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to D9/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. Set the bit 3 of register I2 to "1" for the INT1 pin to be in the input enabled state. Select the valid waveform with the bits 1 and 2 of register I2. Clear the EXF1 flag to "0" with the SNZ1 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. Set both the external 1 interrupt enable bit (V11) and the INTE flag to "1." The external 1 interrupt is now enabled. Now when a valid waveform is input to the D9/INT1 pin, the EXF1 flag is set to "1" and the external 1 interrupt occurs.
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4524 Group
(3) External interrupt control registers
* Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Interrupt control register I1 I13 INT0 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
* Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A.
at reset : 00002
at power down : state retained
R/W TAI1/TI1A
INT0 pin input disabled INT0 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit
Interrupt control register I2 I23 INT1 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAI2/TI2A
INT1 pin input disabled INT1 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI1 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of these bits (I12 , I13, I22 and I23) are changed, the external interrupt request flag (EXF0, EXF1) may be set.
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4524 Group
(4) Notes on External 0 interrupts
Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 18) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 18). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18).
Note on bit 2 of register I1 When the interrupt valid waveform of the D8/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 20) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 20). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20).
***
LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT0 pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 18 External 0 interrupt program example-1 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared, the power down function is selected and the input of INT0 pin is disabled, be careful about the following notes. * When the input of INT0 pin is disabled, invalidate the key-on wakeup function of INT0 pin (register K20 = "0") before system goes into the power down mode. (refer to Figure 19).
: these bits are not used here. Fig. 20 External 0 interrupt program example-3
LA 0 TK2A DI EPOF POF2
***
; (02) ; INT0 key-on wakeup invalid ...........
; RAM back-up
: these bits are not used here. Fig. 19 External 0 interrupt program example-2
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***
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***
4524 Group
(5) Notes on External 1 interrupts
Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes. * Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 21) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 21). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 21).
Note on bit 2 of register I2 When the interrupt valid waveform of the D9/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. * Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 23) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 23). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 23).
***
LA 4 TV1A LA 8 TI2A NOP SNZ1 NOP
; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Control of INT1 pin input is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI2A NOP SNZ1 NOP
***
; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 21 External 1 interrupt program example-1 Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared, the power down function is selected and the input of INT1 pin is disabled, be careful about the following notes. * When the input of INT1 pin is disabled, invalidate the key-on wakeup function of INT1 pin (register K22 = "0") before system goes into the power down mode. (refer to Figure 22).
: these bits are not used here. Fig. 23 External 1 interrupt program example-3
LA 0 TK2A DI EPOF POF2
***
; (02) ; INT1 key-on wakeup invalid ...........
; RAM back-up
: these bits are not used here. Fig. 22 External 1 interrupt program example-2
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4524 Group
TIMERS
The 4524 Group has the following timers. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function).
* Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" after every n count of a count pulse.
FF16 n : Counter initial value Count starts n Reload Reload
The contents of counter
1st underflow
2nd underflow
0016 Time n+1 count "1" Timer interrupt "0" request flag An interrupt occurs or a skip instruction is executed. n+1 count
Fig. 24 Auto-reload function The 4524 Group timer consists of the following circuits. * Prescaler : 8-bit programmable timer * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer * Timer 3 : 8-bit programmable timer * Timer 4 : 8-bit programmable timer * Timer 5 : 16-bit fixed dividing frequency timer * Timer LC : 4-bit programmable timer * Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, 3, 4 and 5 have the interrupt function, respectively) Prescaler and timers 1, 2, 3, 4, 5 and LC can be controlled with the timer control registers PA, W1 to W6. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below.
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Table 9 Function related timers Circuit Prescaler Timer 1 Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT0 input) Count source * Instruction clock (INSTCK) * Instruction clock (INSTCK) * Prescaler output (ORCLK) * Timer 5 underflow (T5UDF) * CNTR0 input Timer 2 8-bit programmable binary down counter * System clock (STCK) * Prescaler output (ORCLK) * Timer 1 underflow (T1UDF) * PWM output (PWMOUT) Timer 3 8-bit programmable binary down counter (link to INT1 input) * PWM output (PWMOUT) * Prescaler output (ORCLK) * Timer 2 underflow (T2UDF) * CNTR1 input Timer 4 8-bit programmable binary down counter Timer 5 * XIN input * Prescaler output (ORCLK) 8192 16384 32768 65536 Timer LC Watchdog timer 4-bit programmable binary down counter 16-bit fixed dividing frequency * Bit 4 of timer 5 * Prescaler output (ORCLK) * Instruction clock (INSTCK) 65534 * System reset (count twice) * WDF flag decision 1 to 16 * LCD clock W6 1 to 256 * Timer 2, 3 count source * CNTR1 output * Timer 4 interrupt * Timer 1, LC count source * Timer 5 interrupt W5 W4 1 to 256 * CNTR1 output control * Timer 3 interrupt W3 1 to 256 * Timer 3 count source * CNTR0 output * Timer 2 interrupt W2 Frequency dividing ratio 1 to 256 1 to 256 Use of output signal * Timer 1, 2, 3, 4 and LC count sources * Timer 2 count source * CNTR0 output * Timer 1 interrupt Control register PA W1 W2
(PWM output function) * XCIN input 16-bit fixed dividing frequency
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Division circuit On-chip oscillator (CMCK) Ceramic resonance Multiplexer (CMCK/CRCK) (Note 1) MR0 0 1 Divided by 8 Divided by4 Divided by 2
MR3, MR2 11 10 01 00 Internal clock generating circuit (divided by 3)
System clock (STCK)
Instruction clock (INSTCK)
XIN
RC oscillation (CRCK)
PA0 (Note 4) 0 Prescaler (8) 1
XCIN
Quartz-crystal oscillation W60 0 Port D7 output W23 0 1 I12 Falling 0 1 Rising I10 W13
ORCLK
D7/CNTR0
1
1/2 1/2
T1UDF T2UDF (TABPS)
Reload register RPS (8) (TPSAB) (TPSAB) (TPSAB) (TABPS)
Register B
Register A
D8/INT0
I13
One-sided edge detection circuit
I11 0 1
(Note 2) SQ
I10 1 0
Both edges detection circuit
R
T1UDF
W11, W10 00 (Note 4) W12 0 1 (TAB1) (T1AB)
Timer 1 (8) Reload register R1 (8)
(TR1AB) (T1AB) (T1AB) (TAB1)
T1F
Timer 1 interrupt
INSTCK ORCLK T5UDF D7/CNTR0
01 10 11
Register B Register A
Timer 1 underflow signal (T1UDF)
W21, W20 00
STCK ORCLK T1UDF PWMOUT
01 10 11
(Note 4) W22 0 1 (TAB2)
Timer 2 (8) Reload register R2 (8)
(T2AB) (T2AB) (T2AB) (TAB2)
T2F
Timer 2 interrupt
Register B Register A
Timer 2 underflow signal (T2UDF)
D9/INT1
I23
I22 Falling 0 1 Rising I20 W33
One-sided edge detection circuit
I21 (Note 3) 0 SQ 1 R
I20 1 0
Both edges detection circuit
T3UDF
W31, W30 00 (Note 4) W32 0 1 (TAB3) (T3AB)
Timer 3 (8) Reload register R3 (8)
(TR3AB) (T3AB) (T3AB) (TAB3)
T3F
Timer 3 interrupt
PWMOUT ORCLK T2UDF C/CNTR1
01 10 11
Register B Register A
Timer 3 underflow signal (T3UDF)
T5UDF: Timer 5 underflow signal (from timer 5) PWMOUT: PWM output signal (from timer 4 output unit)
Data is set automatically from each reload register when timer underflows (auto-reload function).
Notes 1: When CMCK instruction is executed, ceramic resonance is selected. When CRCK instruction is executed, RC oscillation is selected. When any instructions are not executed, on-chip oscillator clock (internal oscillation) is selected. 2: Timer 1 count start synchronous circuit is set by the valid edge of D8/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1. 3: Timer 3 count start synchronous circuit is set by the valid edge of D9/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. 4: Count source is stopped by clearing to "0."
Fig. 25 Timer structure (1)
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Register B
Register A
(T4HAB)
Reload register R4H (8)
(Note 5) W40 0 1 /2 1 (Note 4) W41 0
Reload control circuit
W42
XIN ORCLK
Timer 4 (8)
1 (T4R4L) (T4AB)
"H" interval expansion
1
T
0
Q R
W43
PWMOD
Reload register R4L (8)
(TAB4) (T4AB) (TAB4)
Register B
Register A SIOF
T4F (From Serial I/O) Port C output
I30 0 1
Timer 4, Serial I/O interrupt
PWMOUT (To timer 2 and timer 3) C/CNTR1
W31 W30 W32 (Note 4) W52 0 Q R D T W61
PWMOD
T3UDF
Timer 5 (16) (Note 6) 1 - - 4 - - - - - - - -13 14 15 16 W51, W50 11 10 01 00 (Note 4) W63 0 Timer LC (4) 1
XCIN
1
T5F
Timer 5 interrupt
Timer 5 underflow signal (T5UDF)
W62 0
1/2
LCD clock
ORCLK
1 Reload register RLC (4) (TLCA) (TLCA)
Register A
Watchdog timer (16)
INSTCK
1 - - - - - - - - - - - - - - - - - - - 16 (Note 7) S Q WDF1 R
WRST instruction
Reset signal S Q (Note 9) WEF DWDT instruction R + WRST instruction(Note 8)
D Q WDF2 TR
Watchdog reset signal
Reset signal
INSTCK : Instruction clock (system clock divided by 3) ORCLK : Prescaler output (instruction clock divided by 1 to 256)
Data is set automatically from each reload register when timer underflows (auto-reload function).
Notes 4: Count source is stopped by clearing to "0." 5: XIN cannot be used as count source when bit 1 (MR1) of register MR is set to "1" and f(XIN) oscillation is stopped. 6: This timer is initialized (initial value = FFFF16) by stop of count source (W52 = "0"). 7: Flag WDF1 is cleared to "0" and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = "1". The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = "0". 8: Flag WEF is cleared to "0" and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 9: The WEF flag is set to "1" at system reset or RAM back-up mode.
Fig. 26 Timer structure (2)
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Table 10 Timer related registers Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state initialized) Operating R/W TAW1/TW1A at power down : 02 W TPAA
Timer control register W1 W13 W12 W11 Timer 1 count source selection bits W10 Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit
at reset : 00002 0 1 0 1 W11 W10 0 0 0 1 1 0 1 1
at power down : state retained
Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) Timer 5 underflow signal (T5UDF) CNTR0 input R/W TAW2/TW2A
Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 CNTR0 output control bit Timer 2 control bit
at reset : 00002 0 1 0 1 W21 W20 0 0 0 1 1 0 1 1
at power down : state retained
Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT) R/W TAW3/TW3A
Timer control register W3 W33 W32 W31 Timer 3 count source selection bits (Note 4) Timer 3 count auto-stop circuit selection bit (Note 3) Timer 3 control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
at power down : state retained
W30
Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10="1"). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20="1"). 4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
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Timer control register W4 W43 W42 W41 W40 CNTR1 output control bit PWM signal "H" interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : 00002
R/W TAW4/TW4A
CNTR1 output invalid CNTR1 output valid PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK) divided by 2
Timer control register W5 W53 W52 W51 Timer 5 count value selection bits W50 Not used Timer 5 control bit 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAW5/TW5A
This bit has no function, but read/write is enabled. Stop (state initialized) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts R/W TAW6/TW6A
W51 W50 0 0 0 1 1 0 1 1
Timer control register W6 W63 W62 W61 W60 Timer LC control bit Timer LC count source selection bit CNTR1 output auto-control circuit selection bit D7/CNTR0 pin function selection bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
Stop (state retained) Operating Bit 4 (T54) of timer 5 Prescaler output (ORCLK) CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D7(I/O)/CNTR0 input CNTR0 input/output/D7 (input)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
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(1) Timer control registers
* Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction. * Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. * Timer control register W2 Register W2 controls the selection of CNTR0 output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. * Timer control register W3 Register W3 controls the selection of timer 3 count auto-stop circuit, and the count operation and count source of timer 3. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. * Timer control register W4 Register W4 controls the CNTR1 output, the expansion of "H" interval of PWM output, and the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. * Timer control register W5 Register W5 controls the count operation and count source of timer 5. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A. * Timer control register W6 Register W6 controls the operation and count source of timer LC, the selection of CNTR1 output auto-control circuit and the D7/ CNTR0 pin function. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A..
(2) Prescaler (interrupt function)
Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; set data in prescaler, and set the bit 0 of register PA to "1." When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes "0"), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, 3, 4 and LC count sources.
(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; set data in timer 1 set count source by bits 0 and 1 of register W1, and set the bit 2 of register W1 to "1." When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to "1." Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to "1." Timer 1 underflow signal divided by 2 can be output from CNTR0 pin by clearing bit 3 of register W2 to "0" and setting bit 0 of register W6 to "1".
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(4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; set data in timer 2, select the count source with the bits 0 and 1 of register W2, and set the bit 2 of register W2 to "1." When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 interrupt request flag (T2F) is set to "1," new data is loaded from reload register R2, and count continues (auto-reload function). Timer 2 underflow signal divided by 2 can be output from CNTR0 pin by setting bit 3 of register W2 to "1" and setting bit 0 of register W6 to "1".
(6) Timer 4 (interrupt function)
Timer 4 is an 8-bit binary down counter with two timer 4 reload registers (R4L, R4H). Data can be set simultaneously in timer 4 and the reload register R4L with the T4AB instruction. Data can be set in the reload register R4H with the T4HAB instruction. The contents of reload register R4L set with the T4AB instruction can be set to timer 4 again with the T4R4L instruction. Data can be read from timer 4 with the TAB4 instruction. Stop counting and then execute the T4AB or TAB4 instruction to read or set timer 4 data. When executing the T4HAB instruction to set data to reload register R4H while timer 4 is operating, avoid a timing when timer 4 underflows. Timer 4 starts counting after the following process; set data in timer 4 set count source by bit 0 of register W4, and set the bit 1 of register W4 to "1." When a value set in reload register R4L is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes "0"), the timer 4 interrupt request flag (T4F) is set to "1," new data is loaded from reload register R4L, and count continues (auto-reload function). When bit 3 of register W4 is set to "1", timer 4 reloads data from reload register R4L and R4H alternately each underflow. Timer 4 generates the PWM signal (PWMOUT) of the "L" interval set as reload register R4L, and the "H" interval set as reload register R4H. The PWM signal (PWMOUT) is output from CNTR1 pin. When bit 2 of register W4 is set to "1" at this time, the interval (PWM signal "H" interval) set to reload register R4H for the counter of timer 4 is extended for a half period of count source. In this case, when a value set in reload register R4H is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set "1" or more to reload register R4H. When bit 1 of register W6 is set to "1", the PWM signal output to CNTR1 pin is switched to valid/invalid each timer 3 underflow. However, when timer 3 is stopped (bit 2 of register W3 is cleared to "0"), this function is canceled. Even when bit 1 of a register W4 is cleared to "0" in the "H" interval of PWM signal, timer 4 does not stop until it next timer 4 underflow. When clearing bit 1 of register W4 to "0" to stop timer 4, avoid a timing when timer 4 underflows.
(5) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the TR3AB instruction to set data to reload register R3 while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; set data in timer 3 set count source by bits 0 and 1 of register W3, and set the bit 2 of register W3 to "1." When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes "0"), the timer 3 interrupt request flag (T3F) is set to "1," new data is loaded from reload register R3, and count continues (auto-reload function). INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 0 of register I2 to "1." Also, in this time, the auto-stop function by timer 3 underflow can be performed by setting the bit 3 of register W3 to "1."
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(7) Timer 5 (interrupt function)
Timer 5 is a 16-bit binary down counter. Timer 5 starts counting after the following process; set count value by bits 0 and 1 of register W5, and set the bit 2 of register W5 to "1." Count source for timer 5 is the sub-clock input (XCIN). Once count is started, when timer 5 underflows (the set count value is counted), the timer 5 interrupt request flag (T5F) is set to "1," and count continues. Bit 4 of timer 5 can be used as the timer LC count source for the LCD clock generating. When bit 2 of register W5 is cleared to "0", timer 5 is initialized to "FFFF16" and count is stopped. Timer 5 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When timer 5 underflow occurs at clock operating mode, system returns from the power down state.
(9) Timer input/output pin (D7/CNTR0 pin, C/CNTR1 pin)
CNTR0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. CNTR1 pin is used to input the timer 3 count source and output the PWM signal generated by timer 4. When the PWM signal is output from C/CNTR1 pin, set "0" to the output latch of port C. The D7/CNTR0 pin function can be selected by bit 0 of register W6. The selection of CNTR1 output signal can be controlled by bit 3 of register W4. When the CNTR0 input is selected for timer 1 count source, timer 1 counts the rising waveform of CNTR0 input. When the CNTR1 input is selected for timer 3 count source, timer 3 counts the rising waveform of CNTR1 input. Also, when the CNTR1 input is selected, the output of port C is invalid (high-impedance state).
(8) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data. Timer LC starts counting after the following process; set data in timer LC, select the count source with the bit 2 of register W6, and set the bit 3 of register W6 to "1." When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes "0"), new data is loaded from reload register RLC, and count continues (auto-reload function). Timer LC underflow signal divided by 2 can be used for the LCD clock.
(10) Timer interrupt request flags (T1F, T2F, T3F, T4F, T5F)
Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, SNZT4, SNZT5). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction.
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(11) Count start synchronization circuit (timer 1, timer 3)
Timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of INT0 pin and INT1 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to "1" and the control by INT0 pin input can be performed. Timer 3 count start synchronous circuit function is selected by setting the bit 0 of register I2 to "1" and the control by INT1 pin input can be performed. When timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT0 pin or INT1 pin. The valid waveform of INT0 pin or INT1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 or I20 to "0" or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow.
(13) Precautions
Note the following for the use of timers. * Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. * Timer count source Stop timer 1, 2, 3, 4 and LC counting to change its count source. * Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. * Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its data. * Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. * Timer 4 Avoid a timing when timer 4 underflows to stop timer 4. When "H" interval extension function of the PWM signal is set to be "valid", set "1" or more to reload register R4H. * Timer 5 Stop timer 5 counting to change its count source. * Timer input/output pin Set the port C output latch to "0" to output the PWM signal from C/CNTR pin.
(12) Count auto-stop circuit (timer 1, timer 3)
Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to "1". It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W3 to "1". It is cleared by the timer 3 underflow and the count source to timer 3 is stopped. This function is valid only when the timer 3 count start synchronous circuit is selected.
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q CNTR1 output: invalid (W43 = "0")
Timer 4 count source 0316 (R4L) (R4L) Timer 4 underflow signal PWM signal (output invalid) PWM signal "L" fixed Timer 4 start (R4L) (R4L) (R4L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
Timer 4 count value (Reload register)
q CNTR1 output: valid (W43 = "1") PWM signal "H" interval extension function: invalid (W42 = "0")
Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 start 3 clock PWM period 7 clock 3 clock PWM period 7 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
q CNTR1 output: valid (W43 = "1") PWM signal "H" interval extension function: valid (W42 = "1") (Note)
Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 start 3.5 clock PWM period 7.5 clock 3.5 clock PWM period 7.5 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216
Note: At PWM signal "H" interval extension function: valid, set "0116" or more to reload register R4H.
Fig. 27 Timer 4 operation (reload register R4L: "0316", R4H: "0216")
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CNTR1 output auto-control circuit by timer 3 is selected.
q CNTR1 output: valid (W43 = "1") CNTR1 output auto-control circuit selected (W61 = "1") PWM signal Timer 3 underflow signal Timer 3 start CNTR1 output CNTR1 output start
q CNTR1 output auto-control function
PWM signal Timer 3 underflow signal Timer 3 start Register W61
Timer 3 stop
CNTR1 output CNTR1 output start CNTR1 output stop

When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid, the CNTR1 output invalid state is retained. When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid, the CNTR1 output valid state is retained. When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid. Note: When the PWM signal is output from C/CNTR1 pin, set the output latch of port C to "0".
Fig. 28 CNTR1 output auto-control function by timer 3
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qWaveform extension function of CNTR1 output "H" interval: Invalid (W42 = "0"), CNTR1 output: valid (W43 = "1"), Count source: XIN input selected (W40 = "0"), Reload register R4L: "0316" Reload register R4H: "0216"
Timer 4 count start timing
Machine cycle
Mi
Mi+1
Mi+2
TW4A instruction execution cycle (W41) 1
System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal 0316 (R4L) 0216 0116 0016 0216 0116 0016 0316 0216 0116 (R4H) (R4L)
Timer 4 count start timing
Timer 4 count stop timing
Machine cycle Mi Mi+1 Mi+2
TW4A instruction execution cycle (W41) 0
System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal (Note 1) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R4H) (R4L) 0216 (R4H)
Timer 4 count stop timing
Notes 1: In order to stop timer 4 at CNTR1 output valid (W43 = "1"), avoid a timing when timer 4 underflows. If these timings overlap, a hazard may occur in a CNTR1 output waveform. 2: At CNTR1 output valid, timer 4 stops after "H" interval of PWM signal set by reload register R4H is output.
Fig. 29 Timer 4 count start/stop timing
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4524 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from "FFFF16" after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches "000016," the next count pulse is input), the WDF1 flag is set to "1." If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to "1," and the RESET pin outputs "L" level to reset the microcomputer. Execute the WRST instruction at each period of less than 65534 machine cycle by software when using watchdog timer to keep the microcomputer operating normally.
When the WEF flag is set to "1" after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to "0" and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is "1", the WDF1 flag is cleared to "0" and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is "0", the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid.
FFFF16 Value of 16-bit timer (WDT) 000016 WDF1 flag
65534 count (Note) WDF2 flag
RESET pin output Reset released WRST instruction executed (skip executed) System reset
After system is released from reset (= after program is started), timer WDT starts count down. When timer WDT underflow occurs, WDF1 flag is set to "1." When the WRST instruction is executed, WDF1 flag is cleared to "0," the next instruction is skipped. When timer WDT underflow occurs while WDF1 flag is "1," WDF2 flag is set to "1" and the watchdog reset signal is output. The output transistor of RESET pin is turned "ON" by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock.
Fig. 30 Watchdog timer function
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When the watchdog timer is used, clear the WDF1 flag at a cycle of less than 65534 machine cycles with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 31). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initialize the WDF1 flag with the WRST instruction just before the system enters the power down state (refer to Figure 32). The watchdog timer function is valid after system is returned from the power down. When not using the watchdog timer function, stop the watchdog timer function with the DWDT instruction and the WRST instruction continuously every system is returned from the power down.
WRST
***
; WDF1 flag cleared
DI DWDT WRST
***
; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared
Fig. 31 Program example to start/stop watchdog timer
WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF Oscillation stop
Fig. 32 Program example to enter the mode when using the watchdog timer
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***
***
***
4524 Group
A/D CONVERTER (Comparator)
The 4524 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values.
Table 11 A/D converter characteristics Characteristics Parameter Successive comparison method Conversion format Resolution Relative accuracy Conversion speed Analog input pin 10 bits Linearity error: 2LSB Differential non-linearity error: 0.9LSB 31 s (High-speed through-mode at 6.0 MHz oscillation frequency) 8
Register B (4)
Register A (4) 4 4 IAP2 (P20-P23) IAP3 (P30-P33) OP2A (P20-P23) OP3A (P30-P33) TAQ1 TQ1A 4 TAQ2 TQ2A 4 TAQ3 TQ3A 2
Q13 Q12 Q11 Q10 Q23 Q22 Q21 Q20 Q33 Q32 Q31 Q30
4 4
4
8 TABAD
8 TADAB
TALA
Instruction clock 1/6 3 Q13
0
8-channel multi-plexed analog switch
A/D control circuit
1
P20/AIN0 P21/AIN1 P22/AIN2 P23/AIN3 P30/AIN4 P31/AIN5 P32/AIN6 P33/AIN7
ADF (1)
A/D interrupt
1
Comparator
0
Successive comparison register (AD) (10) 10 10
1
Q13 8
0 1
Q13
DAC operation signal
0
1
Q13
8 DA converter
(Note 1)
8 VDD
8
VSS Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 33 A/D conversion circuit structure
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Table 12 A/D control registers
A/D control register Q1 Q13 A/D operation mode selection bit at reset : 00002 A/D conversion mode Comparator mode Q12 Q11 Q10 0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 0 1 1 AIN3 1 0 0 AIN4 1 0 1 AIN5 1 1 0 AIN6 1 1 1 AIN7 at power down : state retained R/W TAQ1/TQ1A
Analog input pins
Q12
Q11
Analog input pin selection bits
Q10
A/D control register Q2 Q23 Q22 Q21 Q20 P23/AIN3 pin function selection bit P22/AIN2 pin function selection bit P21/AIN1 pin function selection bit P20/AIN0 pin function selection bit 0 1 0 1 0 1 0 1
at reset : 00002 P23 AIN3 P22 AIN2 P21 AIN1 P20 AIN0
at power down : state retained
R/W TAQ2/TQ2A
A/D control register Q3 Q33 Q32 Q31 Q30 P33/AIN7 pin function selection bit P32/AIN6 pin function selection bit P31/AIN5 pin function selection bit P30/AIN4 pin function selection bit 0 1 0 1 0 1 0 1
at reset : 00002 P33 AIN7 P32 AIN6 P31 AIN5 P30 AIN4
at power down : state retained
R/W TAQ3/TQ3A
Note: "R" represents read enabled, and "W" represents write enabled.
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(1) A/D control register
* A/D control register Q1 Register Q1 controls the selection of A/D operation mode and the selection of analog input pins. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. * A/D control register Q2 Register Q2 controls the selection of P20/AIN0-P23/AIN3. Set the contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of register Q2 to register A. * A/D control register Q3 Register Q3 controls the selection of P30/AIN4-P33/AIN7. Set the contents of this register through register A with the TQ3A instruction. The TAQ3 instruction can be used to transfer the contents of register Q3 to register A.
(4) A/D conversion completion flag (ADF)
A/D conversion completion flag (ADF) is set to "1" when A/D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
(5) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD.
(6) Operation description
A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: When the A/D conversion starts, the register AD is cleared to "00016." Next, the topmost bit of the register AD is set to "1," and the comparison voltage Vref is compared with the analog input voltage VIN. When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to "1." When the comparison result is Vref > VIN, it is cleared to "0." The 4524 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conversion stops after 62 machine cycles (31 s when f(XIN) = 6.0 MHz in high-speed through mode) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to "1" as soon as A/D conversion completes (Figure 34).
(2) Operating at A/D conversion mode
The A/D conversion mode is set by setting the bit 3 of register Q1 to "0."
(3) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref =
VDD n 1024
n: The value of register AD (n = 0 to 1023)
Table 13 Change of successive comparison register AD during A/D conversion At starting conversion 1st comparison 2nd comparison 3rd comparison After 10th comparison completes 1: 1st comparison result 3: 3rd comparison result 9: 9th comparison result Change of successive comparison register AD
-------------
Comparison voltage (Vref) value VDD 2 VDD 2 VDD 2 VDD VDD 4 VDD VDD 4

1 1 1
0 1 2
0 0 1
-----------------------------------------------------------------
0 0 0
0 0 0
0 0 0
---------

8 VDD 1024
A/D conversion result
-------------
1
2
3
-------------
-----
8
9
A
2
2: 2nd comparison result 8: 8th comparison result A: 10th comparison result
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(7) A/D conversion timing chart
Figure 34 shows the A/D conversion timing chart.
ADST instruction 62 machine cycles A/D conversion completion flag (ADF) DAC operation signal
Fig. 34 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which the analog input from P30/AIN4 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. Select the AIN4 pin function with the bit 0 of the register Q3. Select the AIN4 pin function and A/D conversion mode with the register Q1 (refer to Figure 35). Execute the ADST instruction and start A/D conversion. Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion. Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0).
(Bit 3)
(Bit 0)
1
A/D control register Q2
AIN4 pin function selected
(Bit 3)
(Bit 0)
0
1
0
0
A/D control register Q1
AIN4 pin selected A/D conversion mode
: Set an arbitrary value.
Fig. 35 Setting registers
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(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to "1." Below, the operation at comparator mode is described.
(12) Comparator operation start instruction (ADST instruction)
In comparator mode, executing ADST starts the comparator operating. The comparator stops 8 machine cycles after it has started (4 s at f(XIN) = 6.0 MHz in high-speed through mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1."
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the 8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 n
(13) Notes for the use of A/D conversion
* TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0." * Operation mode of A/D converter Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. Clear the bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode. The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag.
n: The value of register AD (n = 0 to 255)
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1." The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
ADST instruction 8 machine cycles Comparison result store flag(ADF) DAC operation signal
Comparator operation completed. (The value of ADF is determined)
Fig. 36 Comparator operation timing chart
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(14) Definition of A/D converter accuracy
The A/D conversion accuracy is defined below (refer to Figure 37). * Relative accuracy Zero transition voltage (V0T) This means an analog input voltage when the actual A/D conversion output data changes from "0" to "1." Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from "1023" to "1022." Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. * Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics.
Vn: Analog input voltage when the output data changes from "n" to "n+1" (n = 0 to 1022) * 1LSB at relative accuracy VFST-V0T (V) 1022 VDD 1024
* 1LSB at absolute accuracy
(V)
Output data
1023 1022
Full-scale transition voltage (VFST)
Differential non-linearity error = b-a [LSB] a Linearity error = c [LSB] a
b a
n+1 n
Actual A/D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1-Vn c: Difference between ideal Vn and actual Vn
Ideal line of A/D conversion between V0-V1022
1 0
V0 V1 Zero transition voltage (V0T)
Vn
Vn+1
V1022 Analog voltage
VDD
Fig. 37 Definition of A/D conversion accuracy
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4524 Group
SERIAL I/O
The 4524 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; * serial I/O register SI * serial I/O control register J1 * serial I/O transmit/receive completion flag (SIOF) * serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1.
Table 14 Serial I/O pins Pin D6/SCK D5/SOUT D4/SIN Pin function when selecting serial I/O Clock I/O (SCK) Serial data output (SOUT) Serial data input (SIN)
Note: Even when the SCK, SOUT, SIN pin functions are used, the input of D6, D5, D4 are valid.
1/8 1/4 INSTCK SCK 1/2
J13J12 00 01 10 11
Synchronous circuit
Serial I/O counter (3)
SIOF
Serial I/O interrupt
D6/SCK
Q
S R
SST instruction Internal reset signal
D5/SOUT
SOUT
D4/SIN
SIN
MSB Serial I/O register (8) LSB TABSI J11 J10 TSIAB TABSI
Register B (4)
Register A (4)
Fig. 38 Serial I/O structure Table 15 Serial I/O control register Serial I/O control register J1 at reset : 00002 at power down : state retained R/W TAJ1/TJ1A
J13 J12
J11 J10
J13 J12 Synchronous clock 0 Instruction clock (INSTCK) divided by 8 0 Serial I/O synchronous clock selection bits 0 1 Instruction clock (INSTCK) divided by 4 0 Instruction clock (INSTCK) divided by 2 1 1 External clock (SCK input) 1 J11 J10 Port function 0 D6, D5, D4 selected/SCK, SOUT, SIN not selected 0 Serial I/O port function selection bits 1 SCK, SOUT, D4 selected/D6, D5, SIN not selected 0 0 SCK, D5, SIN selected/D6, SOUT, D4 not selected 1 1 SCK, SOUT, SIN selected/D6, D5, D4 not selected 1
Note: "R" represents read enabled, and "W" represents write enabled.
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At transmit (D7-D0: transfer data)
SIN pin
At receive
SOUT pin
Serial I/O register (SI)
D7 D6 D5 D4 D3 D2 D1 D0
SOUT pin
SIN pin
Serial I/O register (SI)
* ** ** ** *
Transfer data set
D7 D6 D5 D4 D3 D2 D1 D0
* ** ** ** *
D0
* D7 D6 D5 D4 D3 D2 D1 * * D7 D6 D5 D4 D3 D2 * ** ** ** *
Fig. 39 Serial I/O register state when transfer
Transfer start
** ** ** * ******
D1 D0
Transfer complete
D7 D6 D5 D4 D3 D2 D1 D0
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, do not select the SCK pin.
(3) Serial I/O start instruction (SST)
When the SST instruction is executed, the SIOF flag is cleared to "0" and then serial I/O transmission/reception is started.
(4) Serial I/O control register J1
Register J1 controls the synchronous clock, D6/SCK, D5/SOUT and D4/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A.
(2) Serial I/O transmit/receive completion flag (SIOF)
Serial I/O transmit/receive completion flag (SIOF) is set to "1" when serial data transmit or receive operation completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
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(5) How to use serial I/O
Figure 40 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the
Master (clock control)
wiring between each pin with a resistor. Figure 40 shows the data transfer timing and Table 16 shows the data transfer sequence.
Slave (external clock)
D3 SCK SOUT SIN
SRDY signal
D3 SCK SIN SOUT
(Bit 3) 0 0
1
(Bit 0) 1
(Bit 3) Serial I/O control register J1 Serial I/O port SCK,SOUT,SIN
Instruction clock/8 selected as synchronous clock
(Bit 0) 1 1 1 Serial I/O control register J1 Serial I/O port SCK,SOUT,SIN
External clock selected as synchronous clock
1
(Bit 3) 0
(Bit 0) Interrupt control register V2 Serial I/O interrupt enable bit (SNZSI instruction valid)
(Bit 3) 0
(Bit 0) Interrupt control register V2 Serial I/O interrupt enable bit (SNZSI instruction valid)
: Set an arbitrary value.
Fig. 40 Serial I/O connection example
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Master
SOUT SIN SST instruction
M7' S7'
M0 S0
M1 S1
M2 S2
M3 S3
M4 S4
M5 S5
M6 S6
M7 S7
SCK
Slave
SST instruction
SRDY signal SOUT SIN
S7' M7'
S0 M0
S1 M1
S2 M2
S3 M3
S4 M4
S5 M5
S6 M6
S7 M7
M0-M7: Contents of master serial I/O register S0-S7: Contents of slave serial I/O register Rising of SCK: Serial input Falling of SCK: Serial output
Fig. 41 Timing of serial I/O data transfer
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Table 16 Processing sequence of data transfer from master to slave Master (transmission) [Initial setting] * Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 40. TJ1A and TV2A instructions * Setting the port received the reception enable signal (SRDY) to the input mode. (Port D3 is used in this example) SD instruction * [Transmission enable state] * Storing transmission data to serial I/O register SI. TSIAB instruction [Initial setting] * Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 40. TJ1A and TV2A instructions * Setting the port transmitted the reception enable signal (SRDY) and outputting "H" level (reception impossible). (Port D3 is used in this example) SD instruction *[Reception enable state] * The SIOF flag is cleared to "0." SST instruction * "L" level (reception possible) is output from port D3. RD instruction [Transmission] *Check port D3 is "L" level. SZD instruction *Serial transfer starts. SST instruction *Check transmission completes. SNZSI instruction *Wait (timing when continuously transferring) * Check reception completes. SNZSI instruction * "H" level is output from port D3. SD instruction [Data processing] 1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally because serial transmit/receive is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to "1" when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to "H." [Reception] Slave (reception)
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LCD FUNCTION
The 4524 Group has an LCD (Liquid Crystal Display) controller/ driver. When the proper voltage is applied to LCD power supply input pins (VLC1-VLC3) and data are set in timer control register (W6), timer LC, LCD control registers (L1, L2), and LCD RAM, the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. The LCD power input pins (VLC1-VLC3) are also used as pins SEG0-SEG2. When SEG0-SEG2. The internal power (VDD) is used for the LCD power.
(2) LCD clock control
The LCD clock is determined by the timer LC count source selection bit (W62), timer LC control bit (W63), and timer LC. Accordingly, the LCD clock frequency (F) is obtained by the following formula. Numbers ( to ) shown below the formula correspond to numbers in Figure 42, respectively. * When using the prescaler output (ORCLK) as timer LC count source (W62="1") F = ORCLK 1 LC + 1 1 2
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. * 1/2 duty, 1/2 bias * 1/3 duty, 1/3 bias * 1/4 duty, 1/3 bias Table 17 Duty and maximum number of displayed pixels Duty 1/2 1/3 1/4 Maximum number of displayed pixels Used COM pins 40 segments COM0, COM1 (Note) 60 segments COM0-COM2 (Note) 80 segments COM0-COM3
* When using the bit 4 of timer 5 as timer LC count source (W62="0") F = T54 [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = F n n F (Hz) 1 LC + 1 1 2
Frame period =
(s) F: LCD clock frequency 1/n: Duty
Note: Leave unused COM pins open.
(Note) W63 W62 T54 ORCLK 0 1 Reload register RLC (TLCA) (TLCA) (4) 0 1 Timer LC (4) 1/2 LCD clock
Register A Note: Count source is stopped by setting "0" to this bit.
Fig. 42 LCD clock control circuit structure
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VLC3/SEG0 COM3 COM1 COM2 COM0
VLC1/SEG2 SEG3 to SEG19
VLC2/ SEG1
r r r r
SEG0 to SEG2 output
.........
Multiplexer
r r
Control signal
Common driver
Bias control
Segment driver
...
Segment driver
Selector
... Selector ...
RAM
Decoder
1/2,1/3,1/4 counter LCD clock (from timer block)
RAM
LCD ON/OFF control L13 L12 L11 L10 L23 L22 L21 L20
Register A
Fig. 43 LCD controller/driver
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(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display. When "1" is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed.
(4) LCD drive waveform
When "1" is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lVLC3l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common output pin becomes VLC3 level.
Z X Y 8 9 10 11 12 13 14 15 COM
Bits
1 3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM3 2 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM2 12 1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM1 13 0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM0 3 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM3 2 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM2 1 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM1 0 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM0 3 SEG16 SEG17 SEG18 SEG19 14 2 1 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 0 SEG16 SEG17 SEG18 SEG19
COM3 COM2 COM1 COM0
Note: The area marked "
" is not the LCD display RAM.
Fig. 44 LCD RAM map Table 18 LCD control registers LCD control register L1 L13 L12 L11 LCD duty and bias selection bits L10 Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit 0 1 0 1 L11 L10 0 0 0 1 1 0 1 1 at reset : 00002 2r 3, 2r 2 r 3, r 2 Off On Duty Not available 1/2 1/3 1/4 1/2 1/3 1/3 W TL2A Bias at power down : state retained R/W TAL1/TL1A
LCD control register L2 L23 L22 L21 L20 VLC3/SEG0 pin function switch bit (Note 3) VLC2/SEG1 pin function switch bit (Note 4) VLC1/SEG2 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 0 1 0 1 0 1 0 1
at reset : 11112
at power down : state retained
SEG0 VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: "r (resistor) multiplied by 3" is used at 1/3 bias, and "r multiplied by 2" is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
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1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 14, 8) in RAM. 1 flame (2/F) M (1, 14, 8) COM0 COM1 1/F COM1 COM0 SEG16
COM1 SEG16 COM0 SEG16 Voltage level
0 (bit 0) 1 X X (bit 3)
VLC3 VLC1=VLC2 VSS
SEG16
VLC3 VLC1=VLC2 VSS
ON 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM.
OFF
1 flame (3/F) M (1, 14, 8) COM0 COM1 COM2 1/F COM2
Voltage level
1 (bit 0) 0 1 X (bit 3)
COM1
VLC3 VLC2 VLC1 VSS
SEG16 COM0 VLC3 VLC2 VLC1 VSS
SEG16
COM2 SEG16 COM1 SEG16 COM0 SEG16
ON
OFF
ON
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM. 1 flame (4/F) M (1, 14, 8) COM0 COM1 COM2 COM3 SEG16 COM1 1 /F COM3
Voltage level
0 (bit 0) 1 0 1 (bit 3)
COM2
VLC3 VLC2 VLC1 VSS
COM0 VLC3 VLC2 VLC1 VSS
F : LCD clock frequency
SEG16
COM3 SEG16 COM2 SEG16 COM1 SEG16 COM0 SEG16
X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.)
ON
OFF
ON
OFF
Fig. 45 LCD controller/driver structure
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(5) LCD power supply circuit
Select the LCD power circuit suitable for the LCD panel. The LCD control circuit structure is fixed by the following setting. Set the control of internal dividing resistor by bit 0 of register L2. Select the internal dividing resistor by bit 3 of register L1. Select the bias condition by bits 0 and 1 of register L1. * Internal dividing resistor The 4524 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is set to "0", the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to "0", the internal dividing resistor is turned off. The same six resistor (r) is prepared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows; * L13 = "0", 1/3 bias used: 2r 3 = 6r * L13 = "0", 1/2 bias used: 2r 2 = 4r * L13 = "1", 1/3 bias used: r 3 = 3r * L13 = "1", 1/2 bias used: r 2 = 2r
* VLC3/SEG0 pin The selection of VLC3/SEG0 pin function is controlled with the bit 3 of register L2. When the VLC3 pin function is selected, apply voltage of VLC3 < VDD to the pin externally. When the SEG0 pin function is selected, VLC3 is connected to VDD internally. * VLC2/SEG1, VLC1/SEG2 pin The selection of VLC2/SEG1 pin function is controlled with the bit 2 of register L2. The selection of VLC1/SEG2 pin function is controlled with the bit 1 of register L2. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0VLC3
SEG0
VLC3
VLC3
VLC2
SEG1
VLC2
SEG1
VLC1 SEG2
VLC1 SEG2
a) Register L2 = (0000)2
b) Register L2 = (1000)2
VLC3
VLC3
VLC3
VLC3
VLC2
VLC2
VLC2
VLC2
VLC1
VLC1
VLC1
VLC1
c) Register L2 = (1110)2
d) Register L2 = (1111)2
Fig. 46 LCD power source circuit example (1/3 bias condition selected)
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RESET FUNCTION
System reset is performed by applying "L" level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when "H" level is applied to RESET pin, program starts from address 0 in page 0.
f(XIN)
RESET On-chip oscillator (internal oscillator)
is counted 5400 to 5424 times.
Program starts (address 0 in page 0)
Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed.
Fig. 47 Reset release timing
Reset input
=
On-chip oscillator (internal oscillator) is
1 machine cycle or more
counted 5400 to 5424 times.
0.85VDD RESET 0.3VDD
Program starts (address 0 in page 0)
(Note)
Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 48 RESET pin input waveform and reset operation
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(1) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V must be set to 100 s or less. If the rising time ex-
ceeds 100 s, connect a capacitor between the RESET pin and VSS at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
100 s or less
VDD (Note 3)
Pull-up transistor
(Note 1) (Note 2)
Power-on reset circuit output
RESET pin
(Note 1)
Internal reset signal Power-on reset circuit Voltage drop detection circuit Watchdog reset signal
WEF
Internal reset signal
Reset state Power-on Reset released
This symbol represents a parasitic diode. Notes 1: 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 49 Structure of reset pin and its peripherals,, and power-on reset operation Table 19 Port state at reset Name D0-D3 D4/SIN, D5/SOUT, D6/SCK D7/CNTR0 D8/INT0, D9/INT1 P00-P03 P10-P13 P20/AIN0-P23/AIN3 P30/AIN4-P33/AIN7 P40-P43 C/CNTR1
Notes 1: Output latch is set to "1." 2: Output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF.
Function D0-D3 D4-D6 D7 D8, D9 P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 C High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Note 1)
State
High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Note 1) High-impedance (Note 1) High-impedance (Notes 1, 2) "L" (VSS) level
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(2) Internal state at reset
Figure 50 and 51 show internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 50 are undefined, so set the initial value to them.
* Program counter (PC) .......................................................................................................... 0 00000 Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) .................................................................................................. 0 * Power down flag (P) ............................................................................................................. 0 * External 0 interrupt request flag (EXF0) .............................................................................. 0 * External 1 interrupt request flag (EXF1) .............................................................................. 0 * Interrupt control register V1 .................................................................................................. 0 000 * Interrupt control register V2 .................................................................................................. 0 000 * Interrupt control register I1 ................................................................................................... 0 000 * Interrupt control register I2 ................................................................................................... 0 000 * Interrupt control register I3 ................................................................................................... 0 * Timer 1 interrupt request flag (T1F) ..................................................................................... 0 * Timer 2 interrupt request flag (T2F) ..................................................................................... 0 * Timer 3 interrupt request flag (T3F) ..................................................................................... 0 * Timer 4 interrupt request flag (T4F) ..................................................................................... 0 * Timer 5 interrupt request flag (T5F) ..................................................................................... 0 * Watchdog timer flags (WDF1, WDF2) .................................................................................. 0 * Watchdog timer enable flag (WEF) ...................................................................................... 1 * Timer control register PA ...................................................................................................... 0 * Timer control register W1 ..................................................................................................... 0 000 * Timer control register W2 ..................................................................................................... 0 000 * Timer control register W3 ..................................................................................................... 0 000 * Timer control register W4 ..................................................................................................... 0 000 * Timer control register W5 ..................................................................................................... 0 000 * Timer control register W6 ..................................................................................................... 0 000 * Clock control register MR ..................................................................................................... 0 110 * Serial I/O transmit/receive complation flag (SIOF) .............................................................. 0 * Serial I/O mode register J1 .................................................................................................. 0 000 * Serial I/O register SI ............................................................................................................. * A/D conversion completion flag (ADF) ................................................................................. 0 * A/D control register Q1 ......................................................................................................... 0 000 * A/D control register Q2 ......................................................................................................... 0 000 * A/D control register Q3 ......................................................................................................... 0 000 * Successive approximation register AD ................................................................................ * Comparator register .............................................................................................................. * LCD control register L1 ........................................................................................................ 0 000 * LCD control register L2 ........................................................................................................ 1 111
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled) (Interrupt disabled)
(Prescaler stopped) (Timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer 4 stopped) (Timer 5 stopped) (Timer LC stopped)
(External clock selected, serial I/O port not selected)
"" represents undefined. Fig. 50 Internal state at reset
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0000 * Key-on wakeup control register K0 ...................................................................................... 0000 * Key-on wakeup control register K1 ...................................................................................... 0000 * Key-on wakeup control register K2 ...................................................................................... 0000 * Pull-up control register PU0 ................................................................................................. 0000 * Pull-up control register PU1 ................................................................................................. 0000 * Port output structure control register FR0 ........................................................................... 0000 * Port output structure control register FR1 ........................................................................... 0000 * Port output structure control register FR2 ........................................................................... 0000 * Port output structure control register FR3 ........................................................................... 0 * Carry flag (CY) ...................................................................................................................... 0000 * Register A ............................................................................................................................. 0000 * Register B ............................................................................................................................. * Register D ............................................................................................................................. * Register E ............................................................................................................................. 0000 * Register X ............................................................................................................................. 0000 * Register Y ............................................................................................................................. * Register Z ............................................................................................................................. 111 * Stack pointer (SP) ................................................................................................................ * Operation source clock .......................................................... On-chip oscillator (operating) * Ceramic resonator circuit ..................................................................................... Operating * RC oscillation circuit ...................................................................................................... Stop * Quartz-crystal oscillator ........................................................................................ Operating "" represents undefined. Fig. 51 Internal state at reset
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VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value.
The voltage drop detection circuit is valid when CPU is active while the VDCE pin is "H". Even after system goes into the power down mode, the voltage drop detection circuit is also valid with the SVDE instruction. Execution of SVDE instruction is valid only at once. In order to release the execution of the SVDE instruction, system reset is not required.
S Q R EPOF instruction +POF instruction EPOF instruction +POF2 instruction Internal reset signal T5F flag Key-on wakeup signal SVDE instruction Internal reset signal VDCE
Q
S R
- VRST +
Voltage drop detection circuit Reset signal
Voltage drop detection circuit
Fig. 52 Voltage drop detection reset circuit
VDD
VRST (detection voltage)
Voltage drop detection circuit Reset signal Microcomupter starts operation after on-chip oscillator (internal oscillator) clock is counted 5400 to 5424 times.
RESET pin
Note: Detection voltage of voltage drop detection circuit does not have hysteresis.
Fig. 53 Voltage drop detection circuit operation waveform Table 20 Voltage drop detection circuit operation state VDCE pin "L" "H" At CPU operating Invalid Valid At power down (SVDE instruction is not executed) Invalid Invalid
VDD Recommended operatng condition min.value VRST
At power down (SVDE instruction is executed) Invalid Valid
s Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 54); supply voltage does not fall below to VRST, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST and re-goes up after that.
No reset Program failure may occur.
VDD Recommended operatng condition min.value VRST Reset
Normal operation
Fig. 54 VDD and VRST
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POWER DOWN FUNCTION
The 4524 Group has 2-type power down functions. System enters into each power down state by executing the following instructions. * Clock operating mode ...................... EPOF and POF instructions * RAM back-up mode ....................... EPOF and POF2 instructions When the EPOF instruction is not executed before the POF or POF2 instruction is executed, these instructions are equivalent to the NOP instruction.
Table 21 Functions and states retained at power down Power down mode Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control registers I1 to I3 Selected oscillation circuit Clock control register MR Timer 1 to timer 4 functions Timer 5 function Timer LC function Watchdog timer function Timer control registers PA, W4 Timer control registers W1 to W3, W5, W6 Serial I/O function Serial I/O control register J1 A/D function A/D control registers Q1 to Q3 LCD display function LCD control registers L1, L2 Voltage drop detection circuit Port level Pull-up control registers PU0, PU1 Key-on wakeup control registers K0 to K2 Port output format control registers FR0 to FR3 External interrupt request flags (EXF0, EXF1) Timer interrupt request flags (T1F to T4F) (Note 3) O (Note 3) O Timer interrupt request flag (T5F) A/D conversion completion flag (ADF) Serial I/O transmit/receive completion flag SIOF Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) (Note 4) (Note 4) (Note 4) (Note 4)
Clock operating RAM back-up
O O O O (Note 3) O O O O O O O (Note 6) (Note 7) O O O
O O O O (Note 3) O (Note 3) O O O (Note 5) O (Note 6) (Note 7) O O O
(1) Clock operating mode
The following functions and states are retained. * RAM * Reset circuit * XCIN-XCOUT oscillation * LCD display * Timer 5
(Note 4) (Note 4)
(2) RAM back-up mode
The following functions and states are retained. * RAM * Reset circuit
(3) Warm start condition
The system returns from the power down state when; * External wakeup signal is input * Timer 5 underflow occurs in the power down mode. In either case, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is "1."
(4) Cold start condition
The CPU starts executing the program from address 0 in page 0 when; * reset pulse is input to RESET pin, * reset by watchdog timer is performed, or * reset by the voltage drop detection circuit is performed. In this case, the P flag is "0."
(5) Identification of the start condition
Warm start or cold start can be identified by examining the state of the power down flag (P) with the SNZP instruction. The warm start condition from the clock operating mode can be identified by examining the state of T5F flag.
Notes 1:"O" represents that the function can be retained, and "" represents that the function is initialized. Registers and flags other than the above are undefined at power down, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "7" at power down. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then go into the power down state. 5: LCD is turned off. 6: When the SVDE instruction is executed and "H" level is applied to the VDCE pin, this function is valid at power down. 7: In the power down mode, C/CNTR1 pin outputs "L" level. However, when the CNTR input is selected (W11, W10="11"), C/ CNTR1 pin is in an input enabled state (output=high-impedance). Other ports retain their respective output levels.
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(6) Return signal
An external wakeup signal or timer 5 interrupt request flag (T5F) is used to return from the clock operating mode. An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 22 shows the return condition for each return source.
(7) Control registers
* Key-on wakeup control register K0 Register K0 controls the port P0 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K1 Register K1 controls the port P1 key-on wakeup function. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K2 Register K2 controls the INT0 and INT1 pin key-on wakeup function. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A.
* Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. * Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A. * External interrupt control register I1 Register I1 controls the valid waveform of the external 0 interrupt, the input control of INT0 pin and the return input level. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. * External interrupt control register I2 Register I2 controls the valid waveform of the external 1 interrupt, the input control of INT1 pin and the return input level. Set the contents of this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
External wakeup signal
Table 22 Return source and return condition Remarks Return source Return condition Ports P00-P03 Return by an external "L" level in- The key-on wakeup function can be selected by one port unit. Set the port using the key-on wakeup function to "H" level before going into the power Ports P10-P13 put. down state. Return by an external "H" level or Select the return level ("L" level or "H" level) with register I1 (I2) and return INT0 pin "L" level input, or rising edge condition (return by level or edge) with register K2 according to the external INT1 pin ( " L " " H " ) o r f a l l i n g e d g e state before going into the power down state. ("H""L"). When the return signal is input, the interrupt request flag (EXF0, EXF1) is not set to "1". Return by timer 5 underflow or by Clear T5F with the SNZT5 instruction before system enters into the power setting T5F to "1". down state. It can be used in the clock operat- When system enters into the power down state while T5F is "1", system reing mode. turns from the state immediately because it is recognized as return condition.
Timer 5 interrupt request flag (T5F)
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High-speed mode E
Clock operating mode POF instruction execution T5F Wakeup (Stabilizing time c )
B
Operation state * Operation source clock: f(XIN) * Oscillation circuit: Ceramic resonator * On-chip oscillator: Stop * RC oscillation circuit: Stop CMCK instruction execution (Note 3)
POF2 instruction execution
F
RAM back-up mode
Wakeup (Stabilizing time c )
POF instruction execution
Reset
A
Operation state * Operation source clock: f(RING) * Oscillation circuit: On-chip oscillator * Ceramic resonator: Operating (Note 2) * RC oscillation circuit: Stop CRCK instruction execution (Note 3)
POF2 instruction execution
(Stabilizing time a )
T5F Wakeup (Stabilizing time b )
Wakeup (Stabilizing time b )
POF instruction execution T5F Wakeup (Stabilizing time d )
C
Operation state * Operation source clock: f(XIN) * Oscillation circuit: RC oscillation * On-chip oscillator: Stop * Ceramic resontor: Stop
POF2 instruction execution
Wakeup (Stabilizing time d )
Low-speed mode
POF instruction execution T5F Wakeup (Stabilizing time e )
MR01 (Note 4)
MR00 (Note 4)
D
Operation state * Operation clock: f(XCIN) * Oscillation circuit: Quartz-crystal oscillation
POF2 instruction execution
Main clock: stop Sub-clock: operating
Wakeup (Stabilizing time e )
Main clock: stop Sub-clock: stop
Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5400 to 5424 times. Stabilizing time b : In high-speed through-mode, microcomputer starts its operation after counting the f(RING) 675 times. In high-speed/2 mode, microcomputer starts its operation after counting the f(RING) 1350 times. In high-speed/4 mode, microcomputer starts its operation after counting the f(RING) 2700 times. In high-speed/8 mode, microcomputer starts its operation after counting the f(RING) 5400 times. Stabilizing time c : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 675 times. In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 1350 times. In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 2700 times. In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 5400 times. Stabilizing time d : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 21 times. In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 42 times. In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 84 times. In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 168 times. Stabilizing time e : In low-speed through-mode, microcomputer starts its operation after counting the f(XCIN) 675 times. In low-speed/2 mode, microcomputer starts its operation after counting the f(XCIN) 1350 times. In low-speed/4 mode, microcomputer starts its operation after counting the f(XCIN) 2700 times. In low-speed/8 mode, microcomputer starts its operation after counting the f(XCIN) 5400 times. Notes 1: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state. Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state. 2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock. 3: The oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped. 4: The main clock (f(XIN) or f(RING)) or sub-clock (f(XCIN)) is selected for operation source clock by the bit 0 of clock control register MR. 5: The sub-clock (quartz-crystal oscillation) is operating except in state F.
Fig. 55 State transition
Program start
POF or EPOF instruction + POF2 instruction Reset input Power down flag P S Q
P = "1" ? No Cold start
Yes
Warm start
R
POF or q Set source * * * * * * * EPOF instruction + POF2 instruction q Clear source * * * * * * Reset input
T5F = "1" ? No
Yes
Return from timer 5 underflow
Return from external wakeup signal
Fig. 56 Set source and clear source of the P flag
Fig. 57 Start condition identified example using the SNZP instruction
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Table 23 Key-on wakeup control register, pull-up control register and interrupt control register Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained R/W TAK0/ TK0A
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK1/ TK1A
Key-on wakeup control register K1 K13 K12 K11 K10 Port P13 key-on wakeup control bit Port P12 key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002 Key-on wakeup used
at power down : state retained
Key-on wakeup not used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK2/ TK2A
Key-on wakeup control register K2 K23 K22 K21 K20 INT1 pin return condition selection bit INT1 pin key-on wakeup control bit INT0 pin return condition selection bit INT0 pin key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002 Return by level Return by edge
at power down : state retained
Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup not used Key-on wakeup used
Note: "R" represents read enabled, and "W" represents write enabled.
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Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at power down : state retained
R/W TAPU0/ TPU0A
at power down : state retained
R/W TAPU1/ TPU1A
Interrupt control register I1 I13 INT0 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAI1/TI1A
INT0 pin input disabled INT0 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit
Interrupt control register I2 I23 INT1 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAI2/TI2A
INT1 pin input disabled INT1 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI1 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.
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4524 Group
CLOCK CONTROL
The clock control circuit consists of the following circuits. * On-chip oscillator (internal oscillator) * Ceramic resonator * RC oscillation circuit * Quartz-crystal oscillation circuit * Multi-plexer (clock selection circuit) * Frequency divider * Internal clock generating circuit
The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 58 shows the structure of the clock control circuit. The 4524 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator or the RC oscillation can be used for the main clock (f(XIN)) of the 4524 Group. The CMCK instruction or CRCK instruction is executed to select the ceramic resonator or RC oscillator, respectively. The quartz-crystal oscillator can be used for sub-clock (f(XCIN)).
Division circuit Divided by 8 On-chip oscillator (internal oscillator) (Note 1) MR0 0 1 QS QR RC oscillation circuit QS XIN XOUT Divided by 4 Divided by 2
MR3, MR2 11 10 01 00
System clock (STCK) Internal clock generating circuit (divided by 3)
Instruction clock (INSTCK) Wait time control circuit (Note 2) Program start signal
Multi-plexer
CRCK instruction
Ceramic oscillation circuit
R
QS MR1 XCIN XCOUT Quartz-crystal oscillation circuit QS R QS R R
CMCK instruction
Internal reset signal T5F flag Key-on wakeup signal EPOF instruction + POF instruction
EPOF instruction + POF2 instruction
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed after system is released from reset. 2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) or f(XCIN) oscillation. After the certain oscillation stabilizing wait time elapses, the program start signal is output. This circuit operates when system is released from reset or returned from power down.
Fig. 58 Clock control circuit structure
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4524 Group
(1) Main clock generating circuit (f(XIN))
The ceramic resonator or RC oscillation can be used for the main clock of this MCU. After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal oscillator. When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK instruction. The oscillation circuit by the CMCK or CRCK instruction is valid only at once. The oscillation circuit corresponding to the first executed one of these two instructions is valid. Other oscillation circuit and the on-chip oscillator stop. Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). Also, when the CMCK or the CRCK instruction is not executed in prog r a m , t h i s M C U o p e r a t e s b y t h e o n - c h i p o s c i l l a t o r.
Reset On-chip oscillator operation CMCK instruction CRCK instruction
* Ceramic resonator valid * RC oscillation valid * On-chip oscillator stop * On-chip oscillator stop * Ceramic resonator stop * RC oscillation stop
Fig. 59 Switch to ceramic oscillation/RC oscillation
(2) On-chip oscillator operation
When the MCU operates by the on-chip oscillator as the main clock (f(XIN)) without using the ceramic resonator or the RC oscillation, connect XIN pin to VSS and leave XOUT pin open (Figure 60). The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that margin of frequencies when designing application products.
XIN
M34524
the CMCK instruction * Do not use instruction in program. and CRCK
XOUT
Fig. 60 Handling of XIN and XOUT when operating on-chip oscillator
(3) Ceramic resonator
When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. Then, execute the CMCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 61).
XIN
M34524
* Execute the CMCK instruction in program.
XOUT
Note: Externally connect a damping resistor Rd depending on the Rd oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer's recommended value COUT because constants such as capacitance depend on the resonator.
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 62). The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
CIN
Fig. 61 Ceramic resonator external circuit
M34524
R C
XIN
XOUT
* ExsercuuctteiotnhenCpRoCgKam. in t irr
Fig. 62 External RC oscillation circuit
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4524 Group
(5) External clock
When the external clock signal is used as the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open. Then, execute the CMCK instruction (Figure 63). Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the power down function (POF or POF2 instruction) cannot be used when using the external clock.
M34524
* ExsercuuctteiotnhenCpMoCKam. in t i r gr
XOUT VDD VSS
XIN
External oscillation circuit Fig. 63 External clock input circuit
(6) Sub-clock generating circuit f(XCIN)
The quartz-crystal oscillator can be used for the sub-clock signal f(XCIN). Connect a quartz-crystal oscillator and this external circuit to pins XCIN and XCOUT at the shortest distance. A feedback resistor is built in between pins XCIN and XCOUT (Figure 64).
M34524
XCIN
(7) Clock control register MR
Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A.
CIN
Note: Externally connect a damping resistor Rd depending on the oscillation frequency. XCOUT (A feedback resistor is built-in.) Use the quartz-crystal manufacturer's recommended value Rd because constants such as capacitance depend on the resonator. COUT
Table 24 Clock control register MR
Fig. 64 External quartz-crystal circuit R/W TAMR/ TMRA
Clock control register MR MR3 Operation mode selection bits MR2 MR1 MR0 Main clock oscillation circuit control bit System clock selection bit
at reset : 11002 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1
at power down : state retained
Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock oscillation enabled Main clock oscillation stop Main clock (f(XIN) or f(RING)) Sub-clock (f(XCIN))
Note : "R" represents read enabled, and "W" represents write enabled.
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/en/rom).
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4524 Group
LIST OF PRECAUTIONS
Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k (connect this resistor to CNVSS/ VPP pin as close as possible). Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. * Register Z (2 bits) * Register D (3 bits) * Register E (8 bits) Register initial values 2 The initial value of the following registers are undefined at power down. After system is returned from power down, set initial values. * Register Z (2 bits) * Register X (4 bits) * Register Y (4 bits) * Register D (3 bits) * Register E (8 bits) Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. Timer count source Stop timer 1, 2, 3, 4 and LC counting to change its count source. Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its data.
Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows.
10
Timer 4 Avoid a timing when timer 4 underflows to stop timer 4. When "H" interval extension function of the PWM signal is set to be "valid", set "1" or more to reload register R4H. Timer 5 Stop timer 5 counting to change its count source. Timer input/output pin Set the port C output latch to "0" to output the PWM signal from C/CNTR pin.
11
12
13 Watchdog timer * The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction, the WRST instruction continuously, and clear the WEF flag to "0". * The watchdog timer function is valid after system is returned from the power down state. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction and the WRST instruction continuously every system is returned from the power down state. * When the watchdog timer function and power down function are used at the same time, initialize the flag WDF1 with the WRST instruction before system enters into the power down state.
14 Multifunction * Be careful that the output of ports D8 and D9 can be used even when INT0 and INT1 pins are selected. * Be careful that the input of ports D4-D6 can be used even when SIN, SOUT and SCK pins are selected. * Be careful that the input/output of port D7 can be used even when input of CNTR0 pin are selected. * Be careful that the input of port D7 can be used even when output of CNTR0 pin are selected. * Be careful that the "H" output of port C can be used even when output of CNTR1 pin are selected.
15
Program counter Make sure that the PCH does not specify after the last page of the built-in ROM.
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16
D8/INT0 pin Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of register I1 in program, be careful about the following notes. * Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 65) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 65). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 65).
Note on bit 2 of register I1 When the interrupt valid waveform of the D8/INT0 pin is changed with the bit 2 of register I1 in program, be careful about the following notes. * Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 67) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 67). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 67).
***
LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT0 pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 65 External 0 interrupt program example-1 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared, the power down function is selected and the input of INT0 pin is disabled, be careful about the following notes. * When the input of INT0 pin is disabled, invalidate the key-on wakeup function of INT0 pin (register K20 = "0") before system goes into the power down mode. (refer to Figure 66).
: these bits are not used here. Fig. 67 External 0 interrupt program example-3
LA 0 TK2A DI EPOF POF2
***
; (02) ; INT0 key-on wakeup invalid ...........
; RAM back-up
: these bits are not used here. Fig. 66 External 0 interrupt program example-2
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***
page 76 of 159
***
4524 Group
17
D9/INT1 pin Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of register I2 in program, be careful about the following notes. * Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 68) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 68). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 68).
Note on bit 2 of register I2 When the interrupt valid waveform of the D9/INT1 pin is changed with the bit 2 of register I2 in program, be careful about the following notes. * Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 70) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 70). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 70).
***
LA 4 TV1A LA 8 TI2A NOP SNZ1 NOP
; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Control of INT1 pin input is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI2A NOP SNZ1 NOP
***
; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 68 External 1 interrupt program example-1 Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared, the power down function is selected and the input of INT1 pin is disabled, be careful about the following notes. * When the input of INT1 pin is disabled, invalidate the key-on wakeup function of INT1 pin (register K22 = "0") before system goes into the power down mode. (refer to Figure 69).
: these bits are not used here. Fig. 70 External 1 interrupt program example-3
18 A/D converter-1 * When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0." * Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. * Clear the bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode. * The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag.
LA 0 TK2A DI EPOF POF2
***
; (02) ; INT1 key-on wakeup invalid ...........
; RAM back-up LA 8 TV2A LA 0 TQ1A
***
***
***
: these bits are not used here. Fig. 69 External 1 interrupt program example-2
; (02) ; The SNZAD instruction is valid ........ ; (02) ; Operation mode of A/D converter is changed from comparator mode to A/D conversion mode.
SNZAD NOP
***
: these bits are not used here.
Fig. 71 A/D converter program example-3
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19
A/D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins (Figure 72). When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 73. In addition, test the application products sufficiently.
21
POF and POF2 instructions When the POF or POF2 instruction is executed continuously after the EPOF instruction, system enters the power down state. Note that system cannot enter the power down state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF or POF2 instruction continuously. Power-on reset When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to 2.0 V must be set to 100 s or less. If the rising time exceeds 100 s, connect a capacitor between the RESET pin and VSS at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Clock control Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instruction is valid. Other oscillation circuits and the on-chip oscillator stop. On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that margin of frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the oscillation stabilize wait time after system is released from reset, be careful that the margin of frequency of the on-chip oscillator clock. External clock When the external clock signal is used as the main clock (f(XIN)), note that the power down mode (POF or POF2 instruction) cannot be used. Difference between Mask ROM version and One Time PROM version Mask ROM version and One Time PROM version have some difference of the following characteristics within the limits of an electrical property by difference of a manufacture process, builtin ROM, and a layout pattern. * a characteristic value * the amount of noise-proof * a margin of operation * noise radiation, etc., Accordingly, be careful of them when swithcing. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
22
Sensor
AIN
23
Apply the voltage withiin the specifications to an analog input pin.
Fig. 72 Analog input external circuit example-1
About 1k
Sensor
AIN
24
Fig. 73 Analog input external circuit example-2
20
Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 74); supply voltage does not fall below to VRST, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST and re-goes up after that.
VDD Recommended operatng condition min.value VRST
25
26
27
No reset Program failure may occur.
VDD Recommended operatng condition min.value VRST Reset
Normal operation
Fig. 74 VDD and VRST
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4524 Group
CONTROL REGISTERS
Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 R/W TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) R/W TAV2/TV2A
Interrupt control register V2 V23 V22 V21 V20 Timer 4, serial I/O interrupt enable bit A/D interrupt enable bit Timer 5 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : 00002
Interrupt disabled (SNZT4, SNZSI instruction is valid) Interrupt enabled (SNZT4, SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT5 instruction is valid) Interrupt enabled (SNZT5 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) R/W TAI1/TI1A
Interrupt control register I1 I13 INT0 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
INT0 pin input disabled INT0 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit
Interrupt control register I2 I23 INT1 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAI2/TI2A
INT1 pin input disabled INT1 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI1 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected R/W TAI3/TI3A
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit
Interrupt control register I3 I30 Timer 4, serial I/O interrupt source selection bit 0 1
at reset : 02
at power down : state retained
Timer 4 interrupt valid, serial I/O interrupt invalid Serial I/O interrupt valid, timer 4 interrupt invalid
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set to "1".
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4524 Group
Clock control register MR MR3 Operation mode selection bits MR2 MR1 MR0 Main clock oscillation circuit control bit System clock selection bit
at reset : 11002 MR3 MR2 0 0 1 1 0 1 0 1 0 1 0 1
at power down : state retained
R/W TAMR/ TMRA
Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock oscillation enabled Main clock oscillation stop Main clock (f(XIN) or f(RING)) Sub-clock (f(XCIN)) W TPAA
Timer control register PA PA0 Prescaler control bit 0 1
at reset : 02 Stop (state initialized) Operating
at power down : 02
Timer control register W1 W13 W12 W11 Timer 1 count source selection bits W10 Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit
at reset : 00002 0 1 0 1 W11 W10 0 0 0 1 1 0 1 1
at power down : state retained
R/W TAW1/TW1A
Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) Timer 5 underflow signal (T5UDF) CNTR0 input R/W TAW2/TW2A
Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 CNTR0 output control bit Timer 2 control bit
at reset : 00002 0 1 0 1 W21 W20 0 0 0 1 1 0 1 1
at power down : state retained
Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT) R/W TAW3/TW3A
Timer control register W3 W33 W32 W31 Timer 3 count source selection bits (Note 4) Timer 3 count auto-stop circuit selection bit (Note 3) Timer 3 control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
at power down : state retained
W30
Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10="1"). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20="1"). 4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
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4524 Group
Timer control register W4 W43 W42 W41 W40 CNTR1 output control bit PWM signal "H" interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : 00002
R/W TAW4/TW4A
CNTR1 output invalid CNTR1 output valid PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK) divided by 2
Timer control register W5 W53 W52 W51 Timer 5 count value selection bits W50 Not used Timer 5 control bit
at reset : 00002 0 1 0 1 W51 W50 0 0 0 1 1 0 1 1
at power down : state retained
R/W TAW5/TW5A
This bit has no function, but read/write is enabled. Stop (state initialized) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts R/W TAW6/TW6A
Timer control register W6 W63 W62 W61 W60 Timer LC control bit Timer LC count source selection bit CNTR1 output auto-control circuit selection bit D7/CNTR0 pin function selection bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
Stop (state retained) Operating Bit 4 (T54) of timer 5 Prescaler output (ORCLK) CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D7(I/O)/CNTR0 input CNTR0 input/output/D7 (input)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
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4524 Group
Serial I/O control register J1
at reset : 00002
at power down : state retained
R/W TAJ1/TJ1A
J13 J12
J11 J10
Synchronous clock J13 J12 0 Instruction clock (INSTCK) divided by 8 0 Serial I/O synchronous clock selection bits 0 1 Instruction clock (INSTCK) divided by 4 0 Instruction clock (INSTCK) divided by 2 1 1 External clock (SCK input) 1 Port function J11 J10 0 D6, D5, D4 selected/SCK, SOUT, SIN not selected 0 Serial I/O port function selection bits 1 SCK, SOUT, D4 selected/D6, D5, SIN not selected 0 0 SCK, D5, SIN selected/D6, SOUT, D4 not selected 1 1 SCK, SOUT, SIN selected/D6, D5, D4 not selected 1
A/D control register Q1 Q13 A/D operation mode selection bit
at reset : 00002 A/D conversion mode Comparator mode Q12 Q11 Q10 0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 0 1 1 AIN3 1 0 0 AIN4 1 0 1 AIN5 1 1 0 AIN6 1 1 1 AIN7
at power down : state retained
R/W TAQ1/TQ1A
Analog input pins
Q12
Q11
Analog input pin selection bits
Q10
A/D control register Q2 Q23 Q22 Q21 Q20 P23/AIN3 pin function selection bit P22/AIN2 pin function selection bit P21/AIN1 pin function selection bit P20/AIN0 pin function selection bit 0 1 0 1 0 1 0 1
at reset : 00002 P23 AIN3 P22 AIN2 P21 AIN1 P20 AIN0
at power down : state retained
R/W TAQ2/TQ2A
A/D control register Q3 Q33 Q32 Q31 Q30 P33/AIN7 pin function selection bit P32/AIN6 pin function selection bit P31/AIN5 pin function selection bit P30/AIN4 pin function selection bit 0 1 0 1 0 1 0 1
at reset : 00002 P33 AIN7 P32 AIN6 P31 AIN5 P30 AIN4
at power down : state retained
R/W TAQ3/TQ3A
Note: "R" represents read enabled, and "W" represents write enabled.
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4524 Group
LCD control register L1 L13 L12 L11 LCD duty and bias selection bits L10 Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit 0 1 0 1
at reset : 00002 2r 3, 2r 2 r 3, r 2 Off On Duty
at power down : state retained
R/W TAL1/TL1A
L11 L10 0 0 0 1 1 0 1 1
Bias Not available 1/2 1/3 1/3 W TL2A
1/2 1/3 1/4
LCD control register L2 L23 L22 L21 L20 VLC3/SEG0 pin function switch bit (Note 3) VLC2/SEG1 pin function switch bit (Note 4) VLC1/SEG2 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 0 1 0 1 0 1 0 1
at reset : 11112
at power down : state retained
SEG0 VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid R/W TAPU0/ TPU0A
Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at power down : state retained
Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at power down : state retained
R/W TAPU1/ TPU1A
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: "r (resistor) multiplied by 3" is used at 1/3 bias, and "r multiplied by 2" is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
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4524 Group
Port output structure control register FR0 FR03 FR02 FR01 FR00 Ports P12, P13 output structure selection bit Ports P10, P11 output structure selection bit Ports P02, P03 output structure selection bit Ports P00, P01 output structure selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
W TFR0A
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output at reset : 00002 at power down : state retained W TFR1A
Port output structure control register FR1 FR13 FR12 FR11 FR10 Port D3 output structure selection bit Port D2 output structure selection bit Port D1 output structure selection bit Port D0 output structure selection bit 0 1 0 1 0 1 0 1
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR2A
Port output structure control register FR2 FR23 FR22 FR21 FR20 Port D7/CNTR0 output structure selection bit Port D6/SCK output structure selection bit Port D5/SOUT output structure selection bit Port D4/SIN output structure selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR3A
Port output structure control register FR3 FR33 FR32 FR31 FR30 Port P43 output structure selection bit Port P42 output structure selection bit Port P41 output structure selection bit Port P40 output structure selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output
Note: "R" represents read enabled, and "W" represents write enabled.
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4524 Group
Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAK0/ TK0A
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK1/ TK1A
Key-on wakeup control register K1 K13 K12 K11 K10 Port P13 key-on wakeup control bit Port P12 key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 at power down : state retained R/W TAK2/ TK2A
Key-on wakeup control register K2 K23 K22 K21 K20 INT1 pin return condition selection bit INT1 pin key-on wakeup control bit INT0 pin return condition selection bit INT0 pin key-on wakeup control bit 0 1 0 1 0 1 0 1
Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid
Note: "R" represents read enabled, and "W" represents write enabled.
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4524 Group
INSTRUCTIONS
The 4524 Group has the 136 instructions. Each instruction is described as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table Symbol A B DR E V1 V2 I1 I2 I3 MR PA W1 W2 W3 W4 W5 W6 J1 Q1 Q2 Q3 L1 L2 PU0 PU1 FR0 FR1 FR2 FR3 K0 K1 K2 X Y Z DP PC PCH PCL SK SP CY RPS R1 R2 R3 R4L R4H RLC Contents Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Interrupt control register I3 (1 bit) Clock control register MR (4 bits) Timer control register PA (1 bit) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Timer control register W5 (4 bits) Timer control register W6 (4 bits) Serial I/O control register J1 (4 bits) A/D control register Q1 (4 bits) A/D control register Q2 (4 bits) A/D control register Q3 (4 bits) LCD control register L1 (4 bits) LCD control register L2 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Port output format control register FR0 (4 bits) Port output format control register FR1 (4 bits) Port output format control register FR2 (4 bits) Port output format control register FR3 (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits 8) Stack pointer (3 bits) Carry flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 2 reload register (8 bits) Timer 3 reload register (8 bits) Timer 4 reload register (8 bits) Timer 4 reload register (8 bits) Timer LC reload register (4 bits)
SYMBOL
The symbols shown below are used in the following list of instruction function and the machine instructions.
Symbol PS T1 T2 T3 T4 T5 TLC T1F T2F T3F T4F T5F WDF1 WEF INTE EXF0 EXF1 P ADF SIOF D P0 P1 P2 P3 P4 C x y z p n i j A3A2A1A0
Contents Prescaler Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer LC Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Timer 5 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A/D conversion completion flag Serial I/O transmit/receive completion flag Port D (10 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (4 bits) Port P3 (4 bits) Port P4 (4 bits) Port C (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before "?" Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x
? () -- M(DP) a p, a C + x
Note : Some instructions of the 4524 Group has the skip function to unexecute the next described instruction. The 4524 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
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4524 Group
INDEX LIST OF INSTRUCTION FUNCTION
GroupMnemonic ing TAB TBA TAY TYA TEAB (A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) TABE (B) (E7-E4) (A) (E3-E0) TDA TAD (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 TAZ (A1, A0) (Z1, Z0) (A3, A2) 0 AM TAX TASP (A) (X) (A2-A0) (SP2-SP0) (A3) 0 LXY x, y (X) x x = 0 to 15 (Y) y y = 0 to 15 98, 132 120, 132 AMC 118, 132 (A) (A) + (M(DP)) + (CY) (CY) Carry 92, 134 (A) (A) + (M(DP)) 92, 134 121, 132 121, 132 113, 132 112, 132 TABP p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 113, 134 Function Page 111, 132 GroupMnemonic ing XAMI j Function (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 TMA j (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 LA n (A) n n = 0 to 15 98, 134 125, 132 Page 131, 132
121, 132 120, 132 130, 132 121, 132
Register to register transfer
Arithmetic operation
RAM to register transfer
An
(A) (A) + n n = 0 to 15 (A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0
92, 134
RAM addresses
AND OR SC
93, 134 100, 134 104, 134 102, 134 109, 134 95, 134 101, 134
LZ z INY DEY TAM j
(Z) z z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
99, 132 98, 132 95, 132 116, 132
RC SZC CMA RAR
RAM to register transfer
XAM j
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
131, 132
XAMD j
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
131, 132
Note: p is 0 to 63 for M34524M8, p is 0 to 95 for M34524MC and p is 0 to 127 for M34524ED.
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4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic ing SB j Function (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 SZB j (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Ba (PCL) a6-a0 (PCH) p (PCL) a6-a0 BLA p (PCH) p (PCL) (DR2-DR0, A3-A0) BM a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 TV2A TAI1 BML p, a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 BMLA p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) TI3A RTI (PC) (SK(SP)) (SP) (SP) - 1 RT (PC) (SK(SP)) (SP) (SP) - 1 103, 136 103, 136 TPAA TAW1 (PA0) (A0) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) 126, 138 119, 138 129, 138 119, 138 129, 138 119, 138 129, 138 (I30) (A0) 123, 138 TAI3 (A0) (I30), (A3-A1) 0 114, 138 94, 136 TAI2 TI2A (A) (I2) (I2) (A) 114, 138 123, 138 94, 136 TI1A (I1) (A) 123, 138 (V2) (A) (A) (I1) 128, 138 114, 138 94, 136 93, 136 93, 136 SNZI1 BL p, a 93, 136 I22 = 1 : (INT1) = "H" ? I22 = 0 : (INT1) = "L" ? TAV1 TV1A TAV2 (A) (V1) (V1) (A) (A) (V2) 118, 138 128, 138 118, 138 106, 138 109, 134 SNZ1 Page 103, 134 GroupMnemonic ing DI EI RB j 101, 134 SNZ0 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: NOP V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) 0 V11 = 1: NOP SEA n 105, 134 SNZI0 I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ? 106, 138 105, 138 105, 138 (INTE) 0 (INTE) 1 Function Page 96, 138 96, 138
Bit operation
Branch operation
Comparison operation
SEAM
105, 134
Return operation
Subroutine operation
Interrupt operation Timer operation
TW1A TAW2 TW2A TAW3 TW3A
RTS
(PC) (SK(SP)) (SP) (SP) - 1
103, 136
Note: p is 0 to 63 for M34524M8, p is 0 to 95 for M34524MC and p is 0 to 127 for M34524ED.
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4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic TAW4 TW4A TAW5 TW5A TAW6 TW6A TABPS (A) (W4) (W4) (A) (A) (W5) (W5) (A) (A) (W6) (W6) (A) (B) (TPS7-TPS4) (A) (TPS3-TPS0) TPSAB (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) TAB1 (B) (T17-T14) (A) (T13-T10) 111, 140 126, 140 Function Page 119, 138 129, 138 TR1AB 120, 140 130, 140 121, 140 T4R4L 130, 140 (T47-T44) (R4L7-R4L4) (T43-T40) (R4L3-R4L0) 111, 140 TR3AB (R17-R14) (B) (R13-R10) (A) (R37-R34) (B) (R33-R30) (A) 128, 140 127, 140 GroupMnemonic ing T4HAB Function (R4H7-R4H4) (B) (R4H3-R4H0) (A) Page 110, 140
Timer operation
113, 140
TLCA SNZT1
(LC) (A) V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0
125, 140 107, 142
SNZT2
V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0
107, 142
SNZT3
V20 = 0: (T3F) = 1 ? After skipping, (T3F) 0
107, 142
Timer operation
T1AB
(R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A)
109, 140
SNZT4
V23 = 0: (T4F) = 1 ? After skipping, (T4F) 0
108, 142
SNZT5 111, 140 IAP0 110, 140 OP0A IAP1 OP1A
V21 = 0: (T5F) = 1 ? After skipping, (T5F) 0
108, 142
TAB2
(B) (T27-T24) (A) (T23-T20) (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A)
(A) (P0) (P0) (A) (A) (P1) (P1) (A) (A) (P2) (P2) (A) (A) (P3) (P3) (A) (A) (P4) (P4) (A)
97, 142 99, 142 97, 142 99, 142 97, 142 100, 142 97, 142 100, 142 98, 142 100, 142
T2AB
(A) (T33-T30) T3AB (R37-R34) (B) (T37-T34) (B) (R33-R30) (A) (T33-T30) (A) TAB4 (B) (T47-T44) (A) (T43-T40) T4AB (R4L7-R4L4) (B) (T47-T44) (B) (R4L3-R4L0) (A) (T43-T40) (A) 110, 140 112, 140 110, 140
Input/Output operation
TAB3
(B) (T37-T34)
112, 140
IAP2 OP2A IAP3 OP3A IAP4 OP4A
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4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic CLD RD (D) 1 (D(Y)) 0 (Y) = 0 to 9 SD (D(Y)) 1 (Y) = 0 to 9 (D(Y)) = 0 ? (Y) = 0 to 9 104, 142 TABSI 109, 142 TSIAB (B) (SI7-SI4) (A) (SI3-SI0) (SI7-SI4) (B) (SI3-SI0) (A) (SIOF) 0 Serial I/O starting SNZSI V23=0: (SIOF)=1? After skipping, (SIOF) 0 TAJ1 TPU0A (PU0) (A) (A) (PU1) (PU1) (A) (A) (K0) (K0) (A) (A) (K1) (K1) (A) (A) (K2) (K2) (A) (FR0) (A) (FR1) (A) (FR2) (A) (FR3) (A) Ceramic resonator selected RC oscillator selected (A) (MR) (MR) (A) 126, 142 TJ1A TAPU1 TPU1A TAK0 TK0A TAK1 TK1A TAK2 TK2A TFR0A TFR1A TFR2A TFR3A CMCK 117, 142 TABAD 126, 142 124, 144 115, 144 124, 144 115, 144 TADAB 124, 144 115, 144 122, 144 122, 144 122, 144 122, 144 95, 144 95, 144 116, 144 125, 144 ADST (AD7-AD4) (B) (AD3-AD0) (A) (ADF) 0 A/D conversion starting SNZAD V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 TAQ1 TQ1A TAQ2 TQ2A TAQ3 TQ3A (A) (Q1) (Q1) (A) (A) (Q2) (Q2) (A) (A) (Q3) (Q3) (A) 117, 146 127, 146 117, 146 127, 146 118, 146 127, 146 106, 146 92, 146 114, 146 TALA In A/D conversion mode , (B) (AD9-AD6) (A) (AD5-AD2) In comparator mode, (B) (AD7-AD4) (A) (AD3-AD0) (A3, A2) (AD1, AD0) (A1, A0) 0 116, 146 112, 146 (J1) (A) 123, 144 (A) (J1) 115, 144 107, 144 113, 144 128, 144 108, 144 Function Page 94, 142 102, 142 GroupMnemonic ing Function (A) (L1) (L1) (A) (L2) (A) Page 116, 144 124, 144 124, 144 TAL1 TL1A TL2A
SZD
Serial I/O operation A/D operation
LCD operation
SST
RCP SCP TAPU0
(C) 0 (C) 1 (A) (PU0)
102, 142 104, 142 117, 142
Clock operation
Input/Output operation
CRCK TAMR TMRA
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GroupMnemonic ing NOP POF POF2 EPOF SNZP Function (PC) (PC) + 1 Page 99, 146
Transition to clock operating mode 101, 146 Transition to RAM back-up mode POF, POF2 instructions valid (P) = 1 ? Stop of watchdog timer function enabled (WDF1) = 1 ? After skipping, (WDF1) 0 101, 146 96, 146 106, 146 96, 146
Other operation
DWDT
WRST
130, 146
RBK*
When TABP p instruction is ex- 102, 146 ecuted, P6 0 When TABP p instruction is ex- 104, 146 ecuted, P6 1 At power down mode, voltage 108, 146 drop detection circuit valid
SBK*
SVDE
Note: *(RBK, SBK) cannot be used in the M34524M8.
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A n (Add n and accumulator)
Instruction code D9 0 0 0 1 1 0 n n n D0 n
2
0
6
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Overflow = 0
1
Operation:
(A) (A) + n n = 0 to 15
Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation.
ADST (A/D conversion STart)
Instruction code D9 1 0 1 0 0 1 1 1 1 D0 1
2
2
9
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(ADF) 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting (Q13 : bit 3 of A/D control register Q1)
Grouping: A/D conversion operation Description: Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
AM (Add accumulator and Memory)
Instruction code D9 0 0 0 0 0 0 1 0 1 D0 0
2
0
0
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) + (M(DP))
Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction code D9 0 0 0 0 0 0 1 0 1 D0 1
2
0
0
B
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1
Operation:
(A) (A) + (M(DP)) + (CY) (CY) Carry
Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
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AND (logical AND between accumulator and memory)
Instruction code D9 0 0 0 0 0 1 1 0 0 D0 0
2
0
1
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) AND (M(DP))
Grouping: Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
B a (Branch to address a)
Instruction code D9 0 1 1 D0 a6 a5 a4 a3 a2 a1 a0
2
1
8 +a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PCL) a6 to a0
Grouping: Branch operation Description: Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction code D9 0 1 Operation: 0 1 1 1 D0 p4 p3 p2 p1 p0
2
0
2 +p
E +p p +a
p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p6 p5 a6 a5 a4 a3 a2 a1 a0 2
a 16
(PCH) p (PCL) a6 to a0
Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction code D9 0 1 Operation: 0 0 0 0 1 0 0 0 0 D0 0
2
0
2 +p
1 p
0
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p6 p5 p4 0
p3 p2 p1 p0 2
p 16
(PCH) p (PCL) (DR2-DR0, A3-A0)
Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED.
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BM a (Branch and Mark to address a in page 2)
Instruction code D9 0 1 0 D0 a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0
Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
BML p, a (Branch and Mark Long to address a in page p)
Instruction code D9 0 1 Operation: 0 1 1 0 D0 p4 p3 p2 p1 p0
2
0
2 +p
C +p p +a
p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p6 p5 a6 a5 a4 a3 a2 a1 a0 2
a 16
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0
Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction code D9 0 1 Operation: 0 0 0 1 1 0 0 0 0 D0 0
2
0
2 +p
3 p
0
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p6 p5 p4 0
p3 p2 p1 p0 2
p 16
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0)
Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
CLD (CLear port D)
Instruction code D9 0 0 0 0 0 1 0 0 0 D0 1
2
0
1
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D) 1
Grouping: Input/Output operation Description: Sets (1) to port D.
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CMA (CoMplement of Accumulator)
Instruction code D9 0 0 0 0 0 1 1 1 0 D0 02 0 1 C 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (A)
Grouping: Arithmetic operation Description: Stores the one's complement for register A's contents in register A.
CMCK (Clock select: ceraMic oscillation ClocK)
Instruction code D9 1 0 1 0 0 1 1 0 1 D0 0
2
2
9
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Ceramic oscillation circuit selected
Grouping: Other operation Description: Selects the ceramic oscillation circuit and stops the on-chip oscillator.
CRCK (Clock select: Rc oscillation ClocK)
Instruction code D9 1 0 1 0 0 1 1 0 1 D0 1
2
2
9
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
RC oscillation circuit selected
Grouping: Other operation Description: Selects the RC oscillation circuit and stops the on-chip oscillator.
DEY (DEcrement register Y)
Instruction code D9 0 0 0 0 0 1 0 1 1 D0 1
2
0
1
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
1
Operation:
(Y) (Y) - 1
Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
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DI (Disable Interrupt)
Instruction code D9 0 0 0 0 0 0 0 1 0 D0 0
2
0
0
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(INTE) 0
Grouping: Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction code D9 1 0 1 0 0 1 1 1 0 D0 0
2
2
9
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Stop of watchdog timer function enabled
Grouping: Other operation Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
EI (Enable Interrupt)
Instruction code D9 0 0 0 0 0 0 0 1 0 D0 1
2
0
0
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(INTE) 1
Grouping: Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction code D9 0 0 0 1 0 1 1 0 1 D0 1
2
0
5
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
POF instruction, POF2 instruction valid
Grouping: Other operation Description: Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
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IAP0 (Input Accumulator from port P0)
Instruction code D9 1 0 0 1 1 0 0 0 0 D0 0
2
2
6
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P0)
Grouping: Input/Output operation Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction code D9 1 0 0 1 1 0 0 0 0 D0 1
2
2
6
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P1)
Grouping: Input/Output operation Description: Transfers the input of port P1 to register A.
IAP2 (Input Accumulator from port P2)
Instruction code D9 1 0 0 1 1 0 0 0 1 D0 0
2
2
6
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P2)
Grouping: Input/Output operation Description: Transfers the input of port P2 to register A.
IAP3 (Input Accumulator from port P3)
Instruction code D9 1 0 0 1 1 0 0 0 1 D0 1
2
2
6
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P3)
Grouping: Input/Output operation Description: Transfers the input of port P3 to register A.
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IAP4 (Input Accumulator from port P4)
Instruction code D9 1 0 0 1 1 0 0 1 0 D0 02 2 6 4 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (P4)
Grouping: Input/Output operation Description: Transfers the input of port P4 to register A.
INY (INcrement register Y)
Instruction code D9 0 0 0 0 0 1 0 0 1 D0 1
2
0
1
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
1
Operation:
(Y) (Y) + 1
Grouping: RAM addresses Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction code D9 0 0 0 1 1 1 n n n D0 n
2
0
7
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1
Operation:
(A) n n = 0 to 15
Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped.
LXY x, y (Load register X and Y with x and y)
Instruction code D9 1 1 D0 x3 x2 x1 x0 y3 y2 y1 y0
2
3
x
y
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1
Operation:
(X) x x = 0 to 15 (Y) y y = 0 to 15
Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped.
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LZ z (Load register Z with z)
Instruction code D9 0 0 0 1 0 0 1 0 D0 z1 z0 2 0 4 8 +z 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(Z) z z = 0 to 3
Grouping: RAM addresses Description: Loads the value z in the immediate field to register Z.
NOP (No OPeration)
Instruction code D9 0 0 0 0 0 0 0 0 0 D0 0
2
0
0
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PC) (PC) + 1
Grouping: Other operation Description: No operation; Adds 1 to program counter value, and others remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 0 D0 0
2
2
2
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P0) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P0.
OP1A (Output port P1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 0 D0 1
2
2
2
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P1) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P1.
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OP2A (Output port P2 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 1 D0 0
2
2
2
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P2) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P2.
OP3A (Output port P3 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 1 D0 12 2 2 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(P3) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P3.
OP4A (Output port P4 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 1 0 D0 0
2
2
2
4 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(P4) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P4.
OR (logical OR between accumulator and memory)
Instruction code D9 0 0 0 0 0 1 1 0 0 D0 1
2
0
1
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) OR (M(DP))
Grouping: Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A.
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POF (Power OFf1)
Instruction code D9 0 0 0 0 0 0 0 0 1 D0 0
2
0
0
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Transition to clock operating mode
Grouping: Other operation Description: Puts the system in clock operating state by executing the POF instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction.
POF2 (Power OFf2)
Instruction code D9 0 0 0 0 0 0 1 0 0 D0 0
2
0
0
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Transition to RAM back-up mode
Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction.
RAR (Rotate Accumulator Right)
Instruction code D9 0 0 0 0 0 1 1 1 0 D0 1
2
0
1
D
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1
Operation:
CY A3A2A1A0
Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
RB j (Reset Bit)
Instruction code D9 0 0 0 1 0 0 1 1 j D0 j
2
0
4
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) 0 j = 0 to 3
Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
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RBK (Reset Bank flag)
Instruction code D9 0 0 0 1 0 0 0 0 0 D0 0
2
0
4
0 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
When TABP p instruction is executed, P6 0
Grouping: Other operation Description: Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. Note: This instruction cannot be used in M34524M8.
RC (Reset Carry flag)
Instruction code D9 0 0 0 0 0 0 0 1 1 D0 0
2
0
0
6 16
Number of words 1
Number of cycles 1
Flag CY 0
Skip condition -
Operation:
(CY) 0
Grouping: Arithmetic operation Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruction code D9 1 0 1 0 0 0 1 1 0 D0 0
2
2
8
C 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(C) 0
Grouping: Input/Output operation Description: Clears (0) to port C.
RD (Reset port D specified by register Y)
Instruction code D9 0 0 0 0 0 1 0 1 0 D0 02 0 1 4 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(D(Y)) 0 However, (Y) = 0 to 9
Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y.
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RT (ReTurn from subroutine)
Instruction code D9 0 0 0 1 0 0 0 1 0 D0 0
2
0
4
4
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine.
RTI (ReTurn from Interrupt)
Instruction code D9 0 0 0 1 0 0 0 1 1 D0 0
2
0
4
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction code D9 0 0 0 1 0 0 0 1 0 D0 1
2
0
4
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition Skip at uncondition
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instruction code D9 0 0 0 1 0 1 1 1 j D0 j
2
0
5
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) 1 j = 0 to 3
Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
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SBK (Set Bank flag)
Instruction code D9 0 0 0 1 0 0 0 0 0 D0 1
2
0
4
1 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
When TABP p instruction is executed, P6 1
Grouping: Other operation Description: Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. Note: This instruction cannot be used in M34524M8. In M34524MC, referring data area is pages 64 to 95.
SC (Set Carry flag)
Instruction code D9 0 0 0 0 0 0 0 1 1 D0 1
2
0
0
7
Number of words
16
Number of cycles 1
Flag CY 1
Skip condition -
1
Operation:
(CY) 1
Grouping: Arithmetic operation Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruction code D9 1 0 1 0 0 0 1 1 0 D0 1
2
2
8
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(C) 1
Grouping: Input/Output operation Description: Sets (1) to port C.
SD (Set port D specified by register Y)
Instruction code D9 0 0 0 0 0 1 0 1 0 D0 1
2
0
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D(Y)) 1 (Y) = 0 to 9
Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y.
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SEA n (Skip Equal, Accumulator with immediate data n)
Instruction code D9 0 0 Operation: 0 0 0 0 0 1 1 1 0 1 0 n 1 n 0 n D0 1
2
0 0
2 7
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (A) = n
2
n2
(A) = n ? n = 0 to 15
n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.
SEAM (Skip Equal, Accumulator with Memory)
Instruction code D9 0 0 0 0 1 0 0 1 1 D0 0
2
0
2
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (A) = (M(DP))
1
Operation:
(A) = (M(DP)) ?
Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction code D9 0 0 0 0 1 1 1 0 0 D0 0
2
0
3
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V10 = 0: (EXF0) = 1
1
Operation:
V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1)
Grouping: Interrupt operation Description: When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is "1." After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is "0," executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction.
SNZ1 (Skip if Non Zero condition of external 1 interrupt request flag)
Instruction code D9 0 0 0 0 1 1 1 0 0 D0 1
2
0
3
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V11 = 0: (EXF1) = 1
1
Operation:
V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) 0 V11 = 1: SNZ1 = NOP (V11 : bit 1 of the interrupt control register V1)
Grouping: Interrupt operation Description: When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is "1." After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is "0," executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction.
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SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Instruction code D9 1 0 1 0 0 0 0 1 1 D0 1
2
2
8
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V22 = 0: (ADF) = 1
1
Operation:
V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 V22 = 1: SNZAD = NOP (V22 : bit 2 of the interrupt control register V2)
Grouping: A/D conversion operation Description: When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is "1." After skipping, clears (0) to the ADF flag. When the ADF flag is "0," executes the next instruction. When V22 = 1 : This instruction is equivalent to the NOP instruction.
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction code D9 0 0 0 0 1 1 1 0 1 D0 02 0 3 A 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition I12 = 0 : (INT0) = "L" I12 = 1 : (INT0) = "H"
Operation:
I12 = 0 : (INT0) = "L" ? I12 = 1 : (INT0) = "H" ? (I12 : bit 2 of the interrupt control register I1)
Grouping: Interrupt operation Description: When I12 = 0 : Skips the next instruction when the level of INT0 pin is "L." Executes the next instruction when the level of INT0 pin is "H." When I12 = 1 : Skips the next instruction when the level of INT0 pin is "H." Executes the next instruction when the level of INT0 pin is "L." Number of words 1 Number of cycles 1 Flag CY - Skip condition I22 = 0 : (INT1) = "L" I22 = 1 : (INT1) = "H"
SNZI1 (Skip if Non Zero condition of external 1 Interrupt input pin)
Instruction code D9 0 0 0 0 1 1 1 0 1 D0 12 0 3 B 16
Operation:
I22 = 0 : (INT1) = "L" ? I22 = 1 : (INT1) = "H" ? (I22 : bit 2 of the interrupt control register I2)
Grouping: Interrupt operation Description: When I22 = 0 : Skips the next instruction when the level of INT1 pin is "L." Executes the next instruction when the level of INT1 pin is "H." When I22 = 1 : Skips the next instruction when the level of INT1 pin is "H." Executes the next instruction when the level of INT1 pin is "L." Number of words
16
SNZP (Skip if Non Zero condition of Power down flag)
Instruction code D9 0 0 0 0 0 0 0 0 1 D0 1
2
0
0
3
Number of cycles 1
Flag CY -
Skip condition (P) = 1
1
Operation:
(P) = 1 ?
Grouping: Other operation Description: Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is "0."
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SNZSI (Skip if Non Zero condition of Serial I/o interrupt request flag)
Instruction code D9 1 0 1 0 0 0 1 0 0 D0 0
2
2
8
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V23 = 0: (SIOF) = 1
1
Operation:
V23 = 0: (SIOF) = 1 ? After skipping, (SIOF) 0 V23 = 1: SNZSI = NOP (V23 = bit 3 of interrupt control register V2)
Grouping: Serial I/O operation Description: When V23 = 0 : Skips the next instruction when serial I/O interrupt request flag SIOF is "1." After skipping, clears (0) to the SIOF flag. When the SIOF flag is "0," executes the next instruction. When V23 = 1 : This instruction is equivalent to the NOP instruction.
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 0 D0 0
2
2
8
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V12 = 0: (T1F) = 1
1
Operation:
V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1)
Grouping: Timer operation Description: When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is "1." After skipping, clears (0) to the T1F flag. When the T1F flag is "0," executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 0 D0 1
2
2
8
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V13 = 0: (T2F) = 1
1
Operation:
V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1)
Grouping: Timer operation Description: When V13 = 0 : Skips the next instruction when timer 2 interrupt request flag T2F is "1." After skipping, clears (0) to the T2F flag. When the T2F flag is "0," executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction.
SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 1 D0 0
2
2
8
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V20 = 0: (T3F) = 1
1
Operation:
V20 = 0: (T3F) = 1 ? After skipping, (T3F) 0 V20 = 1: SNZT3 = NOP (V20 = bit 0 of interrupt control register V2)
Grouping: Timer operation Description: When V20 = 0 : Skips the next instruction when timer 3 interrupt request flag T3F is "1." After skipping, clears (0) to the T3F flag. When the T3F flag is "0," executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction.
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SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 1 D0 1
2
2
8
3 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition V23 = 0: (T4F) = 1
Operation:
V23 = 0: (T4F) = 1 ? After skipping, (T4F) 0 V23 = 1: SNZT4 = NOP (V23 = bit 3 of interrupt control register V2)
Grouping: Timer operation Description: When V23 = 0 : Skips the next instruction when timer 4 interrupt request flag T4F is "1." After skipping, clears (0) to the T4F flag. When the T4F flag is "0," executes the next instruction. When V23 = 1 : This instruction is equivalent to the NOP instruction.
SNZT5 (Skip if Non Zero condition of Timer 5 inerrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 1 0 D0 0
2
2
8
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V21 = 0: (T5F) = 1
1
Operation:
V21 = 0: (T5F) = 1 ? After skipping, (T5F) 0 V21 = 1: SNZT5 = NOP (V21 = bit 1 of interrupt control register V2)
Grouping: Timer operation Description: When V21 = 0 : Skips the next instruction when timer 5 interrupt request flag T5F is "1." After skipping, clears (0) to the T5F flag. When the T5F flag is "0," executes the next instruction. When V21 = 1 : This instruction is equivalent to the NOP instruction.
SST (Serial i/o transmission/reception STart)
Instruction code D9 1 0 1 0 0 1 1 1 1 D0 0
2
2
9
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(SIOF) 0 Serial I/O transmission/reception start
Grouping: Serial I/O operation Description: Clears (0) to SIOF flag and starts serial I/O.
SVDE (Set Voltage Detector Enable flag)
Instruction code D9 1 0 1 0 0 1 0 0 1 D0 1
2
2
9
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
At power down mode, voltage drop detection circuit valid
Grouping: Other operation Description: Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode) when VDCE pin is "H".
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SZB j (Skip if Zero, Bit)
Instruction code D9 0 0 0 0 1 0 0 0 j D0 j
2
0
2
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Mj(DP)) = 0 j = 0 to 3
1
Operation:
(Mj(DP)) = 0 ? j = 0 to 3
Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Executes the next instruction when the contents of bit j of M(DP) is "1."
SZC (Skip if Zero, Carry flag)
Instruction code D9 0 0 0 0 1 0 1 1 1 D0 1
2
0
2
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (CY) = 0
1
Operation:
(CY) = 0 ?
Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is "0." After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is "1."
SZD (Skip if Zero, port D specified by register Y)
Instruction code D9 0 0 Operation: 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 D0 0
2
0 0
2 2
4
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (D(Y)) = 0
(Y) = 0 to 7
2
12
B 16
(D(Y)) = 0 ? (Y) = 0 to 7
Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is "0." Executes the next instruction when the bit is "1."
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 0 D0 0
2
2
3
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(T17-T14) (B) (R17-R14) (B) (T13-T10) (A) (R13-R10) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
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T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 0 D0 1
2
2
3
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(T27-T24) (B) (R27-R24) (B) (T23-T20) (A) (R23-R20) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 1 D0 02 2 3 2 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(T37-T34) (B) (R37-R34) (B) (T33-T30) (A) (R33-R30) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3.
T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 1 D0 12 2 3 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(T47-T44) (B) (R4L7-R4L4) (B) (T43-T40) (A) (R4L3-R4L0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L.
T4HAB (Transfer data to register R4H from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 1 1 D0 1
2
2
3
7 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(R4H7-R4H4) (B) (R4H3-R4H0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4H. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4H.
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T4R4L (Transfer data to timer 4 from register R4L)
Instruction code D9 1 0 1 0 0 1 0 1 1 D0 1
2
2
9
7 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(T47-T44) (R4L7-R4L4) (T43-T40) (R4L3-R4L0)
Grouping: Timer operation Description: Transfers the contents of reload register R4L to timer 4.
TAB (Transfer data to Accumulator from register B)
Instruction code D9 0 0 0 0 0 1 1 1 1 D0 0
2
0
1
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (B)
Grouping: Register to register transfer Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction code D9 1 0 0 1 1 1 0 0 0 D0 0
2
2
7
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T17-T14) (A) (T13-T10)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T17-T14) of timer 1 to register B. Transfers the low-order 4 bits (T13-T10) of timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction code D9 1 0 0 1 1 1 0 0 0 D0 1
2
2
7
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T27-T24) (A) (T23-T20)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T27-T24) of timer 2 to register B. Transfers the low-order 4 bits (T23-T20) of timer 2 to register A.
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TAB3 (Transfer data to Accumulator and register B from timer 3)
Instruction code D9 1 0 0 1 1 1 0 0 1 D0 0
2
2
7
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T37-T34) (A) (T33-T30)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T37-T34) of timer 3 to register B. Transfers the low-order 4 bits (T33-T30) of timer 3 to register A.
TAB4 (Transfer data to Accumulator and register B from timer 4)
Instruction code D9 1 0 0 1 1 1 0 0 1 D0 1
2
2
7
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T47-T44) (A) (T43-T40)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T47-T44) of timer 4 to register B. Transfers the low-order 4 bits (T43-T40) of timer 4 to register A.
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction code D9 1 0 0 1 1 1 1 0 0 D0 1
2
2
7
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
In A/D conversion mode (Q13 = 0), (B) (AD9-AD6) (A) (AD5-AD2) In comparator mode (Q13 = 1), (B) (AD7-AD4) (A) (AD3-AD0) (Q13 : bit 3 of A/D control register Q1)
Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9-AD6) of register AD to register B, and the middle-order 4 bits (AD5-AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7-AD4) of register AD to register B, and the low-order 4 bits (AD3-AD0) of register AD to register A. D0 Number of words
16
TABE (Transfer data to Accumulator and register B from register E)
Instruction code D9 0 0 0 0 1 0 1 0 1 0
2
0
2
A
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (E7-E4) (A) (E3-E0)
Grouping: Register to register transfer Description: Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits of register E to register A.
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TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction code D9 0 0 1 0 D0 p5 p4 p3 p2 p1 p0
2
0
8 +p
p 16
Number of words 1
Number of cycles 3
Flag CY -
Skip condition -
Operation:
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1
Grouping: Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. The pages which can be referred as follows; after the SBK instruction: 64 to 127 after the RBK instruction: 0 to 63 after system is released from reset or returned from power down: 0 to 63. Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. D0 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
TABPS (Transfer data to Accumulator and register B from PreScaler)
Instruction code D9 1 0 0 1 1 1 0 1 0 1
2
2
7
5 16
Operation:
(B) (TPS7-TPS4) (A) (TPS3-TPS0)
Grouping: Timer operation Description: Transfers the high-order 4 bits (TPS7- TPS4) of prescaler to register B, and transfers the low-order 4 bits (TPS3-TPS0) of prescaler to register A.
TABSI (Transfer data to Accumulator and register B from register SI)
Instruction code D9 1 0 0 1 1 1 1 0 0 D0 0
2
2
7
8 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(B) (SI7-SI4) (A) (SI3-SI0)
Grouping: Serial I/O operation Description: Transfers the high-order 4 bits (SI7-SI4) of serial I/O register SI to register B, and transfers the low-order 4 bits (SI3-SI0) of serial I/O register SI to register A.
TAD (Transfer data to Accumulator from register D)
Instruction code D9 0 0 0 1 0 1 0 0 0 D0 1
2
0
5
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A2-A0) (DR2-DR0) (A3) 0
Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. Note: When this instruction is executed, "0" is stored to the bit 3 (A3) of register A.
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TADAB (Transfer data to register AD from Accumulator from register B)
Instruction code D9 1 0 0 0 1 1 1 0 0 D0 1
2
2
3
9 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(AD7-AD4) (B) (AD3-AD0) (A)
Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7-AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3-AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) D0 Number of words
16
TAI1 (Transfer data to Accumulator from register I1)
Instruction code D9 1 0 0 1 0 1 0 0 1 1
2
2
5
3
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (I1)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I1 to register A.
TAI2 (Transfer data to Accumulator from register I2)
Instruction code D9 1 0 0 1 0 1 0 1 0 D0 0
2
2
5
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (I2)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I2 to register A.
TAI3 (Transfer data to Accumulator from register I3)
Instruction code D9 1 0 0 1 0 1 0 1 0 D0 1
2
2
5
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A0) (I30) (A3-A1) 0
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I3 to the lowermost bit (A0) of register A. Note: When the TAI3 instruction is executed, "0" is stored to the high-order 3 bits (A3-A1) of register A.
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TAJ1 (Transfer data to Accumulator from register J1)
Instruction code D9 1 0 0 1 0 0 0 0 1 D0 0
2
2
4
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (J1)
Grouping: Serial I/O operation Description: Transfers the contents of serial I/O control register J1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction code D9 1 0 0 1 0 1 0 1 1 D0 0
2
2
5
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K0)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A.
TAK1 (Transfer data to Accumulator from register K1)
Instruction code D9 1 0 0 1 0 1 1 0 0 D0 1
2
2
5
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K1)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A.
TAK2 (Transfer data to Accumulator from register K2)
Instruction code D9 1 0 0 1 0 1 1 0 1 D0 0
2
2
5
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K2)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A.
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TAL1 (Transfer data to Accumulator from register L1)
Instruction code D9 1 0 0 1 0 0 1 0 1 D0 0
2
2
4
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (L1)
Grouping: LCD control operation Description: Transfers the LCD control register L1 to register A.
TALA (Transfer data to Accumulator from register LA)
Instruction code D9 1 0 0 1 0 0 1 0 0 D0 1
2
2
4
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A3, A2) (AD1, AD0) (A1, A0) 0
Grouping: A/D conversion operation Description: Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A. Note: After this instruction is executed, "0" is stored to the low-order 2 bits (A1, A0) of register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction code D9 1 0 1 1 0 0 j j j D0 j
2
2
C
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
TAMR (Transfer data to Accumulator from register MR)
Instruction code D9 1 0 0 1 0 1 0 0 1 D0 0
2
2
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (MR)
Grouping: Clock operation Description: Transfers the contents of clock control register MR to register A.
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TAPU0 (Transfer data to Accumulator from register PU0)
Instruction code D9 1 0 0 1 0 1 0 1 1 D0 1
2
2
5
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (PU0)
Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU0 to register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction code D9 1 0 0 1 0 1 1 1 1 D0 0
2
2
5
E 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (PU1)
Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU1 to register A.
TAQ1 (Transfer data to Accumulator from register Q1)
Instruction code D9 1 0 0 1 0 0 0 1 0 D0 0
2
2
4
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (Q1)
Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q1 to register A.
TAQ2 (Transfer data to Accumulator from register Q2)
Instruction code D9 1 0 0 1 0 0 0 1 0 D0 1
2
2
4
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (Q2)
Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q2 to register A.
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TAQ3 (Transfer data to Accumulator from register Q3)
Instruction code D9 1 0 0 1 0 0 0 1 1 D0 0
2
2
4
6 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (Q3)
Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q3 to register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction code D9 0 0 0 1 0 1 0 0 0 D0 0
2
0
5
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A2-A0) (SP2-SP0) (A3) 0
Grouping: Register to register transfer Description: Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. Note: After this instruction is executed, "0" is stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruction code D9 0 0 0 1 0 1 0 1 0 D0 0
2
0
5
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (V1)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V1 to register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction code D9 0 0 0 1 0 1 0 1 0 D0 1
2
0
5
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (V2)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V2 to register A.
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TAW1 (Transfer data to Accumulator from register W1)
Instruction code D9 1 0 0 1 0 0 1 0 1 D0 1
2
2
4
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W1)
Grouping: Timer operation Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction code D9 1 0 0 1 0 0 1 1 0 D0 0
2
2
4
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W2)
Grouping: Timer operation Description: Transfers the contents of timer control register W2 to register A.
TAW3 (Transfer data to Accumulator from register W3)
Instruction code D9 1 0 0 1 0 0 1 1 0 D0 1
2
2
4
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W3)
Grouping: Timer operation Description: Transfers the contents of timer control register W3 to register A.
TAW4 (Transfer data to Accumulator from register W4)
Instruction code D9 1 0 0 1 0 0 1 1 1 D0 0
2
2
4
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W4)
Grouping: Timer operation Description: Transfers the contents of timer control register W4 to register A.
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TAW5 (Transfer data to Accumulator from register W5)
Instruction code D9 1 0 0 1 0 0 1 1 1 D0 1
2
2
4
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W5)
Grouping: Timer operation Description: Transfers the contents of timer control register W5 to register A.
TAW6 (Transfer data to Accumulator from register W6)
Instruction code D9 1 0 0 1 0 1 0 0 0 D0 0
2
2
5
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W6)
Grouping: Timer operation Description: Transfers the contents of timer control register W6 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction code D9 0 0 0 1 0 1 0 0 1 D0 0
2
0
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (X)
Grouping: Register to register transfer Description: Transfers the contents of register X to register A.
TAY (Transfer data to Accumulator from register Y)
Instruction code D9 0 0 0 0 0 1 1 1 1 D0 1
2
0
1
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (Y)
Grouping: Register to register transfer Description: Transfers the contents of register Y to register A.
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TAZ (Transfer data to Accumulator from register Z)
Instruction code D9 0 0 0 1 0 1 0 0 1 D0 12 0 5 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A1, A0) (Z1, Z0) (A3, A2) 0
Grouping: Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, "0" is stored to the high-order 2 bits (A3, A2) of register A.
TBA (Transfer data to register B from Accumulator)
Instruction code D9 0 0 0 0 0 0 1 1 1 D0 0
2
0
0
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (A)
Grouping: Register to register transfer Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instruction code D9 0 0 0 0 1 0 1 0 0 D0 1
2
0
2
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(DR2-DR0) (A2-A0)
Grouping: Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D.
TEAB (Transfer data to register E from Accumulator and register B)
Instruction code D9 0 0 0 0 0 1 1 0 1 D0 0
2
0
1
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(E7-E4) (B) (E3-E0) (A)
Grouping: Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E7-E4) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E.
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TFR0A (Transfer data to register FR0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 0 D0 02 2 2 8 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(FR0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR0.
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 0 D0 1
2
2
2
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(FR1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR1.
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 1 D0 0
2
2
2
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(FR2) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR2.
TFR3A (Transfer data to register FR3 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 1 D0 1
2
2
2
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(FR3) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR3.
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TI1A (Transfer data to register I1 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 1 D0 1
2
2
1
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(I1) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I1.
TI2A (Transfer data to register I2 from Accumulator)
Instruction code D9 1 0 0 0 0 1 1 0 0 D0 0
2
2
1
8 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(I2) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I2.
TI3A (Transfer data to register I3 from Accumulator)
Instruction code D9 1 0 0 0 0 1 1 0 1 D0 0
2
2
1
A 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(I30) (A0)
Grouping: Interrupt operation Description: Transfers the contents of the lowermost bit (A0) of register A to interrupt control register I1.
TJ1A (Transfer data to register J1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 0 0 1 D0 0
2
2
0
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(J1) (A)
Grouping: Serial I/O operation Description: Transfers the contents of register A to serial I/O control register J1.
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TK0A (Transfer data to register K0 from Accumulator)
Instruction code D9 1 0 0 0 0 1 1 0 1 D0 1
2
2
1
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 0 D0 0
2
2
1
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K1.
TK2A (Transfer data to register K2 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 0 D0 1
2
2
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K2) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K2.
TL1A (Transfer data to register L1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 0 1 D0 0
2
2
0
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(L1) (A)
Grouping: LCD operation Description: Transfers the contents of register A to LCD control register L1.
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TL2A (Transfer data to register L2 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 0 1 D0 12 2 0 B 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(L2) (A)
Grouping: LCD operation Description: Transfers the contents of register A to LCD control register L2.
TLCA (Transfer data to timer LC and register RLC from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 0 D0 1
2
2
0
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(LC) (A) (RLC) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer LC and reload register RLC.
TMA j (Transfer data to Memory from Accumulator)
Instruction code D9 1 0 1 0 1 1 j j j D0 j
2
2
B
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 1 D0 0
2
2
1
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(MR) (A)
Grouping: Other operation Description: Transfers the contents of register A to clock control register MR.
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TPAA (Transfer data to register PA from Accumulator)
Instruction code D9 1 0 1 0 1 0 1 0 1 D0 0
2
2
A
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PA0) (A0)
Grouping: Timer operation Description: Transfers the contents of lowermost bit (A0) register A to timer control register PA.
TPSAB (Transfer data to Pre-Scaler from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 1 0 D0 1
2
2
3
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 0 D0 1
2
2
2
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 1 D0 0
2
2
2
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU1.
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TQ1A (Transfer data to register Q1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 0 1 0 D0 0
2
2
0
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Q1) (A)
Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q1.
TQ2A (Transfer data to register Q2 from Accumulator)
Instruction code D9 1 0 0 0 0 0 0 1 0 D0 1
2
2
0
5 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Q2) (A)
Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q2.
TQ3A (Transfer data to register Q3 from Accumulator)
Instruction code D9 1 0 0 0 0 0 0 1 1 D0 0
2
2
0
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Q3) (A)
Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q3.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 1 1 1 D0 1
2
2
3
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(R17-R14) (B) (R13-R10) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R17-R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13-R10) of reload register R1.
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TR3AB (Transfer data to register R3 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 1 0 1 D0 1
2
2
3
B 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(R37-R34) (B) (R33-R30) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R37-R34) of reload register R3, and the contents of register A to the low-order 4 bits (R33-R30) of reload register R3.
TSIAB (Transfer data to register SI from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 1 0 0 D0 0
2
2
3
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(SI7-SI4) (B) (SI3-SI0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (SI7-SI4) of serial I/O register SI, and transfers the contents of register A to the low-order 4 bits (SI3-SI0) of serial I/O register SI.
TV1A (Transfer data to register V1 from Accumulator)
Instruction code D9 0 0 0 0 1 1 1 1 1 D0 1
2
0
3
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(V1) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction code D9 0 0 0 0 1 1 1 1 1 D0 02 0 3 E 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(V2) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V2.
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TW1A (Transfer data to register W1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 1 D0 02 2 0 E 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(W1) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W1.
TW2A (Transfer data to register W2 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 1 D0 1
2
2
0
F 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(W2) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W2.
TW3A (Transfer data to register W3 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 0 D0 0
2
2
1
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W3) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W3.
TW4A (Transfer data to register W4 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 0 D0 1
2
2
1
1 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(W4) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W4.
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TW5A (Transfer data to register W5 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 1 D0 0
2
2
1
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W5) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W5.
TW6A (Transfer data to register W6 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 1 D0 12 2 1 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(W6) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W6.
TYA (Transfer data to register Y from Accumulator)
Instruction code D9 0 0 0 0 0 0 1 1 0 D0 0
2
0
0
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Y) (A)
Grouping: Register to register transfer Description: Transfers the contents of register A to register Y.
WRST (Watchdog timer ReSeT)
Instruction code D9 1 0 1 0 1 0 0 0 0 D0 0
2
2
A
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (WDF1) = 1
1
Operation:
(WDF1) = 1 ? After skipping, (WDF1) 0
Grouping: Other operation Description: Skips the next instruction when watchdog timer flag WDF1 is "1." After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is "0," executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
XAM j (eXchange Accumulator and Memory data)
Instruction code D9 1 0 1 1 0 1 j j j D0 j
2
2
D
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction code D9 1 0 1 1 1 1 j j j D0 j
2
2
F
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. D0 Number of words
16
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction code D9 1 0 1 1 1 0 j j j j
2
2
E
j
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. D0
2 16
Instruction code
D9
Number of words
Number of cycles
Flag CY
Skip condition
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4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0
01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
(A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x x = 0 to 15 (Y) y y = 0 to 15 (Z) z z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1
Register to register transfer
TEAB TABE TDA TAD TAZ TAX TASP LXY x, y
x3 x2 x1 x0 y3 y2 y1 y0
RAM addresses
LZ z INY DEY
0 0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 1 1
1 0 0
0 0 1
z1 z0 1 1 1 1
048 +z 013 017
1 1 1
1 1 1
TAM j
1
0
1
1
0
0
j
j
j
j
2Cj
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2Dj
1
1
RAM to register transfer
XAMD j
1
0
1
1
1
1
j
j
j
j
2Fj
1
1
XAMI j
1
0
1
1
1
0
j
j
j
j
2Ej
1
1
TMA j
1
0
1
0
1
1
j
j
j
j
2Bj
1
1
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4524 Group
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - Continuous description - (Y) = 0 (Y) = 15
- - - - - - - - - - - -
Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E7-E4) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E. Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits (E3-E0) of register E to register A. Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
- - -
-
-
-
-
(Y) = 15
-
(Y) = 0
-
-
-
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4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 0 0 1 1 1 n n n n
07n
1
1
(A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (A) (A) + (M(DP)) (A) (A) + (M(DP)) +(CY) (CY) Carry (A) (A) + n n = 0 to 15
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
08p +p
1
3
AM
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 0
1 1 n
0 0 n
1 1 n
0 1 n
00A 00B 06n
1 1 1
1 1 1
Arithmetic operation
AMC An
AND OR SC RC SZC CMA RAR SB j
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 0
0 0 0 0 1 0 0 0 0 1
1 1 0 0 0 1 1 1 0 0
1 1 0 0 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 0 0 j j j
0 1 1 0 1 0 1 j j j
018 019 007 006 02F 01C 01D 05C +j 04C +j 02j
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
(A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ?
Bit operation
RB j SZB j
SEAM
0
0
0
0
1
0
0
1
1
0
026
1
1
Comparison operation
SEA n
0 0
0 0
0 0
0 1
1 1
0 1
0 n
1 n
0 n
1 n
025 07n
2
2
(A) = n ? n = 0 to 15
Note: p is 0 to 63 for M34524M8, p is 0 to 95 for M34524MC and p is 0 to 127 for M34524ED.
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4524 Group
Skip condition
Carry flag CY
Datailed description
Continuous description -
-
Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. The pages which can be referred as follows; after the SBK instruction: 64 to 127 after the RBK instruction: 0 to 63 after system is released from reset or returned from power down: 0 to 63. Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
-
- - Overflow = 0
-
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. - Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is "0." Stores the one's complement for register A's contents in register A.
- - - - (CY) = 0 - - - - (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP))
- - 1 0 - -
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. - - - Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Executes the next instruction when the contents of bit j of M(DP) is "1." Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.
-
(A) = n
-
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4524 Group
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ba BL p, a 0 0 1 BLA p 0 1 BM a 0 1 0 1 1 a6 a5 a4 a3 a2 a1 a0 1 1 p4 p3 p2 p1 p0
18a +a 0Ep +p 2pa +p +a 010 2pp +p 1aa
1 2
1 2
(PCL) a6-a0 (PCH) p (Note) (PCL) a6-a0
Branch operation
p6 p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 1 0 0 0 0 0
2
2
(PCH) p (Note) (PCL) (DR2-DR0, A3-A0)
p6 p5 p4 0 1 0
p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
1
1
Subroutine operation
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0,A3-A0) (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1
BML p, a
0 1
0
1
1
0
p4 p3 p2 p1 p0
0Cp +p 2pa +p +a 030 2pp +p 046
2
2
p6 p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 1 1 0 0 0 0 0
BMLA p
0 1
2
2
p6 p5 p4 0
p3 p2 p1 p0
RTI
0
0
0
1
0
0
0
1
1
0
1
1
Return operation
RT
0
0
0
1
0
0
0
1
0
0
044
1
2
RTS
0
0
0
1
0
0
0
1
0
1
045
1
2
Note: p is 0 to 63 for M34524M8, p is 0 to 95 for M34524MC and p is 0 to 127 for M34524ED.
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4524 Group
Skip condition
Carry flag CY
Datailed description
- -
- -
Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p.
-
-
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
-
-
Call the subroutine : Calls the subroutine at address a in page p.
-
-
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine.
-
-
Skip at uncondition
-
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
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4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DI EI SNZ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0
004 005 038
1 1 1
1 1 1
(INTE) 0 (INTE) 1 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: SNZ0 = NOP V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) 0 V11 = 1: SNZ1 = NOP I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ?
SNZ1
0
0
0
0
1
1
1
0
0
1
039
1
1
SNZI0
0
0
0
0
1
1
1
0
1
0
03A
1
1
Interrupt operation
SNZI1
0
0
0
0
1
1
1
0
1
1
03B
1
1
I22 = 1 : (INT1) = "H" ? I22 = 0 : (INT1) = "L" ?
TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TAI3 TI3A TPAA TAW1 TW1A
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0
0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1
0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0
1 1 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 0
0 1 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1
054 03F 055 03E 253 217 254 218 255 21A 2AA 24B 20E 24C 20F 24D 210 24E 211
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A) (A) (I2) (I2) (A) (A0) (I30), (A3-A1) 0 (I30) (A0) (PA0) (A0) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) (A) (W4) (W4) (A)
Timer operation
TAW2 TW2A TAW3 TW3A TAW4 TW4A
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4524 Group
Skip condition
Carry flag CY
Datailed description
- - V10 = 0: (EXF0) = 1
- - -
Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is "1." After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is "0," executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is "1." After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is "0," executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1) When I12 = 1 : Skips the next instruction when the level of INT0 pin is "H." (I12: bit 2 of interrupt control register I1) When I12 = 0 : Skips the next instruction when the level of INT0 pin is "L."
V11 = 0: (EXF1) = 1
-
(INT0) = "H" However, I12 = 1 (INT0) = "L" However, I12 = 0 (INT1) = "H" However, I22 = 1 (INT1) = "L" However, I22 = 0 - - - - - - - - - - - - - - - - - - -
- -
- - - - - - - - - - - - - - - - - - - - -
When I22 = 1 : Skips the next instruction when the level of INT1 pin is "H." (I22: bit 2 of interrupt control register I2) When I22 = 0 : Skips the next instruction when the level of INT1 pin is "L." Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of interrupt control register I3 to the lowermost bit (A0) of register A. Transfers the contents of the lowermost bit (A0) of register A to interrupt control register I3. Transfers the contents of register A to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4.
Rev.2.00 Jul 27, 2004 REJ03B0091-0200Z
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4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAW5 TW5A TAW6 TW6A TABPS TPSAB 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 1
24F 212 250 213 275 235
1 1 1 1 1 1
1 1 1 1 1 1
(A) (W5) (W5) (A) (A) (W6) (W6) (A) (B) (TPS7-TPS4) (A) (TPS3-TPS0) (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) (B) (T17-T14) (A) (T13-T10) (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) (B) (T27-T24) (A) (T23-T20) (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A) (B) (T37-T34) (A) (T33-T30) (R37-R34) (B) (T37-T34) (B) (R33-R30) (A) (T33-T30) (A) (B) (T47-T44) (A) (T43-T40) (R4L7-R4L4) (B) (T47-T44) (B) (R4L3-R4L0) (A) (T43-T40) (A) (R4H7-R4H4) (B) (R4H3-R4H0) (A) (R17-R14) (B) (R13-R10) (A) (R37-R34) (B) (R33-R30) (A) (T47-T40) (R4L7-R4L0) (LC) (A) (RLC) (A)
TAB1 T1AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
0 0
270 230
1 1
1 1
TAB2 T2AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
1 1
271 231
1 1
1 1
Timer operation
TAB3 T3AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
1 1
0 0
272 232
1 1
1 1
TAB4 T4AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
1 1
1 1
273 233
1 1
1 1
T4HAB TR1AB TR3AB T4R4L TLCA
1 1 1 1 1
0 0 0 0 0
0 0 0 1 0
0 0 0 0 0
1 1 1 0 0
1 1 1 1 0
0 1 1 0 1
1 1 0 1 1
1 1 1 1 0
1 1 1 1 1
237 23F 23B 297 20D
1 1 1 1 1
1 1 1 1 1
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4524 Group
Skip condition
Carry flag CY
Datailed description
- - - - - -
- - - - - -
Transfers the contents of timer control register W5 to register A. Transfers the contents of register A to timer control register W5. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
- -
- -
- -
- -
Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2, and transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
- -
- -
Transfers the high-order 4 bits of timer 3 to register B, and transfers the low-order 4 bits of timer 3 to register A. Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3.
- -
- -
Transfers the high-order 4 bits of timer 4 to register B, and transfers the low-order 4 bits of timer 4 to register A. Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L, and transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L.
- - - - -
- - - - -
Transfers the contents of register B to the high-order 4 bits of timer 4 reload register R4H, and transfers the contents of register A to the low-order 4 bits of timer 4 reload register R4H. Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 reload register R1. Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 reload register R3. Transfers the contents of timer 4 reload register R4L to timer 4. Transfers the contents of register A to timer LC and timer LC reload register RLC.
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4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SNZT1 SNZT2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 RCP SCP TAPU0 TPU0A TAPU1 TPU1A 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0
280 281 282 283 284 260 220 261 221 262 222 263 223 264 224 011 014 015 024 02B 28C 28D 257 22D 25E 22E
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0 V12 = 1: NOP V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0 V13 = 1: NOP V20 = 0: (T3F) = 1 ? After skipping, (T3F) 0 V20 = 1: NOP V23 = 0: (T4F) = 1 ? After skipping, (T4F) 0 V23 = 1: NOP V21 = 0: (T5F) = 1 ? After skipping, (T5F) 0 V21 = 1: NOP (A) (P0) (P0) (A) (A) (P1) (P1) (A) (A) (P2) (P2) (A) (A) (P3) (P3) (A) (A) (P4) (P4) (A) (D) 1 (D(Y)) 0 (Y) = 0 to 9 (D(Y)) 1 (Y) = 0 to 9 (D(Y)) = 0 ? (Y) = 0 to 7 (C) 0 (C) 1 (A) (PU0) (PU0) (A) (A) (PU1) (PU1) (A)
Timer operation Input/Output operation
SNZT3 SNZT4 SNZT5 IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A IAP4 OP4A CLD RD SD SZD
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4524 Group
Skip condition
Carry flag CY
Datailed description
V12 = 0: (T1F) = 1 V13 = 0: (T2F) =1 V20 = 0: (T3F) = 1 V23 = 0: (T4F) =1 V21 = 0: (T5F) =1 - - - - - - - - - - - - - (D(Y)) = 0 However, (Y)=0 to 7 - - - - - -
- - - - - - - - - - - - - - - - - - -
Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is "0" and the contents of T1F flag is "1." After skipping, clears (0) to T1F flag. Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is "0" and the contents of T2F flag is "1." After skipping, clears (0) to T2F flag. Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is "0" and the contents of T3F flag is "1." After skipping, clears (0) to T3F flag. Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is "0" and the contents of T4F flag is "1." After skipping, clears (0) to T4F flag. Skips the next instruction when the contents of bit 1 (V21) of interrupt control register V2 is "0" and the contents of T5F flag is "1." After skipping, clears (0) to T5F flag. Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Outputs the contents of register A to port P2. Transfers the input of port P3 to register A. Outputs the contents of register A to port P3. Transfers the input of port P4 to register A. Outputs the contents of register A to port P4. Sets (1) to all port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is "0." Executes the next instruction when a bit of port D specified by register Y is "1." Clears (0) to port C. Sets (1) to port C. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1.
- - - - - -
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4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAK0 TK0A TAK1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0
256 21B 259 214 25A 215 228 229 22A 22B 24A 20A 20B 278 238 29E 288 242 202 29A 29B 252 216
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (K0) (K0) (A) (A) (K1) (K1) (A) (A) (K2) (K2) (A) (FR0) (A) (FR1) (A) (FR2) (A) (FR3) (A) (A) (L1) (L1) (A) (L2) (A) (B) (SI7-SI4) (A) (SI3-SI0) (SI7-SI4) (B) (SI3-SI0) (A) (SIOF) 0 Serial I/O starting V23=0: (SIOF)=1? After skipping, (SIOF) 0 V23 = 1: NOP (A) (J1) (J1) (A) Ceramic resonator selected RC oscillator selected (A) (MR) (MR) (A)
Input/Output operation LCD operation Serial I/O operation Clock operation
TK1A TAK2 TK2A TFR0A TFR1A TFR2A TFR3A TAL1 TL1A TL2A TABSI TSIAB SST SNZSI TAJ1 TJ1A CMCK CRCK TAMR TMRA
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4524 Group
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - - - - - - V23 = 0: (SIOF) = 1 - - - - - -
- - - - - - - - - - - - - - - - - - - - - - -
Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0 . Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transferts the contents of register A to port output format control register FR0. Transferts the contents of register A to port output format control register FR1. Transferts the contents of register A to port output format control register FR2. Transferts the contents of register A to port output format control register FR3. Transfers the contents of LCD control register L1 to register A. Transfers the contents of register A to LCD control register L1. Transfers the contents of register A to LCD control register L2. Transfers the high-order 4 bits of serial I/O register SI to register B, and transfers the low-order 4 bits of serial I/O register SI to register A. Transfers the contents of register B to the high-order 4 bits of serial I/O register SI, and transfers the contents of register A to the low-order 4 bits of serial I/O register SI. Clears (0) to SIOF flag and starts serial I/O. Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is "0" and contents of SIOF flag is "1." After skipping, clears (0) to SIOF flag. Transfers the contents of serial I/O control register J1 to register A. Transfers the contents of register A to serial I/O control register J1. Selects the ceramic resonator for main clock, stops the on-chip oscillator (internal oscillator). Selects the RC oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator). Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR.
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4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TABAD 1 0 0 1 1 1 1 0 0 1
279
1
1
Q13 = 0: (B) (AD9-AD6) (A) (AD5-AD2) Q13 = 1: (B) (AD7-AD4) (A) (AD3-AD0) (A3, A2) (AD1, AD0) (A1, A0) 0 (AD7-AD4) (B) (AD3-AD0) (A) (ADF) 0 A/D conversion starting V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 V22 = 1: NOP (A) (Q1) (Q1) (A) (A) (Q2) (Q2) (A) (A) (Q3) (Q3) (A) (PC) (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode POF, POF2 instructions valid (P) = 1 ? (WDF1) = 1 ? After skipping, (WDF1) 0 Stop of watchdog timer function enabled When TABP p instruction is executed, P6 0 When TABP p instruction is executed, P6 1 At power down mode, voltage drop detection circuit valid
TALA TADAB
1 1
0 0
0 0
1 0
0 1
0 1
1 1
0 0
0 0
1 1
249 239
1 1
1 1
A/D conversion operation
ADST
1
0
1
0
0
1
1
1
1
1
29F
1
1
SNZAD
1
0
1
0
0
0
0
1
1
1
287
1
1
TAQ1 TQ1A TAQ2 TQ2A TAQ3 TQ3A NOP POF POF2 EPOF SNZP
1 1 1 1 1 1 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1
1 0 1 0 1 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 1 1 0 0
1 1 1 1 1 1 0 0 0 0 0 0
0 0 0 0 1 1 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 1 1 0
244 204 245 205 246 206 000 002 008 05B 003 2A0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
Other operation
WRST
DWDT RBK* SBK* SVDE
1 0 0 1
0 0 0 0
1 0 0 1
0 1 1 0
0 0 0 0
1 0 0 1
1 0 0 0
1 0 0 0
0 0 0 1
0 0 1 1
29C 040 041 293
1 1 1 1
1 1 1 1
Note: * (SBK, RBK) cannot be used in the M34524M8. The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 95 in the M34524MC.
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4524 Group
Skip condition
Carry flag CY
Datailed description
-
-
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9-AD6) of register AD to register B, and the middle-order 4 bits (AD5-AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7-AD4) of register AD to register B, and the low-order 4 bits (AD3-AD0) of register AD to register A. (Q13: bit 3 of A/D control register Q1) Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7-AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3-AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. (Q13 = bit 3 of A/D control register Q1) When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is "1." After skipping, clears (0) to the ADF flag. When the ADF flag is "0," executes the next instruction. (V22: bit 2 of interrupt control register V2) Transfers the contents of A/D control register Q1 to register A. Transfers the contents of register A to A/D control register Q1. Transfers the contents of A/D control register Q2 to register A. Transfers the contents of register A to A/D control register Q2. Transfers the contents of A/D control register Q3 to register A. Transfers the contents of register A to A/D control register Q3. No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction. Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Skips the next instruction when watchdog timer flag WDF1 is "1." After skipping, clears (0) to the WDF1 flag. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode) when VDCE pin is "H".
- -
- -
-
-
V22 = 0: (ADF) = 1
-
- - - - - - - - - - (P) = 1 (WDF1) = 1
- - - - - - - - - - - -
- - - -
- - - -
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4524 Group
INSTRUCTION CODE TABLE
D9-D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011001100 001101 001110 001111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
010000 011000 010111 011111
00 NOP - POF
01 BLA CLD -
02
03
04
05
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A
0B
0C
0D BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML
0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
10-17 18-1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B
SZB BMLA RBK** TASP 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM - - - - - - - - - SNZ0 SBK** TAD - - RT TAX TAZ TAV1
TABP TABP TABP TABP BML 32* 48* 0 16 TABP TABP TABP TABP BML 33* 49* 1 17 TABP TABP TABP TABP BML 34* 50* 2 18 TABP TABP TABP TABP BML 35* 51* 3 19 TABP TABP TABP TABP BML 36* 52* 4 20 TABP TABP TABP TABP BML 37* 53* 5 21 TABP TABP TABP TABP BML 38* 54* 6 22 TABP TABP TABP TABP BML 39* 55* 7 23 TABP TABP TABP TABP BML 40* 56* 8 24 TABP TABP TABP TABP BML 41* 57* 9 25 TABP TABP TABP TABP BML 42* 58* 10 26 TABP TABP TABP TABP BML 43* 59* 11 27 TABP TABP TABP TABP BML 44* 60* 12 28 TABP TABP TABP TABP BML 45* 61* 13 29 TABP TABP TABP TABP BML 46* 62* 14 30 TABP TABP TABP TABP BML 47* 63* 15 31
SNZP INY DI EI RC SC RD SD - DEY
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - - - - EPOF SB 0 SB 1 SB 2 SB 3
POF2 AND - AM AMC TYA - TBA - OR
TDA SNZ1
TEAB TABE SNZI0 - CMA RAR TAB TAY - - - - SNZI1 - - TV2A
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 * ** (SBK and RBK instructions) cannot be used in the M34524M8. * * cannot be used after the SBK instruction is executed in the M34524MC. * A page referred by the TABP instruction can be switched by the SBK and RBK instructions in the M34524MC/ED. * The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 95 in the M34524MC. * The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 127 in the M34524ED. (Ex. TABP 0 TABP 64) * The pages which can be referred by the TABP instruction after the RBK instruction is executed are 0 to 63. * When the SBK instruction is not used, the pages which can be referred by the TABP instruction are 0 to 63.
BL BML BLA BMLA SEA SZD
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4524 Group
INSTRUCTION CODE TABLE (continued)
D9-D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
110000 111111
20 - -
21
22
23
24 - -
25
26
27
28
29 - - -
2A WRST - - - - - - - - -
2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15
2C TAM 0 TAM 1 TAM 2 TAM 3 TAM 4 TAM 5 TAM 6 TAM 7 TAM 8 TAM 9 TAM 10 TAM 11 TAM 12 TAM 13 TAM 14 TAM 15
2D
2E
2F
30-3F
TW3A OP0A T1AB TW4A OP1A T2AB
TAW6 IAP0 TAB1 SNZT1 - IAP1 TAB2 SNZT2
XAM XAMI XAMD LXY 0 0 0 XAM XAMI XAMD LXY 1 1 1 XAM XAMI XAMD LXY 2 2 2 XAM XAMI XAMD LXY 3 3 3 XAM XAMI XAMD LXY 4 4 4 XAM XAMI XAMD LXY 5 5 5 XAM XAMI XAMD LXY 6 6 6 XAM XAMI XAMD LXY 7 7 7 XAM XAMI XAMD LXY 8 8 8 XAM XAMI XAMD LXY 9 9 9 XAM XAMI XAMD LXY 10 10 10 XAM XAMI XAMD LXY 11 11 11 XAM XAMI XAMD LXY 12 12 12 XAM XAMI XAMD LXY 13 13 13 XAM XAMI XAMD LXY 14 14 14 XAM XAMI XAMD LXY 15 15 15
TJ1A TW5A OP2A T3AB TAJ1 TAMR IAP2 TAB3 SNZT3 - TW6A OP3A T4AB - - TAI1
IAP3 TAB4 SNZT4 SVDE IAP4 - - - - - - - - - - - - TABPS - - SNZT5 - - - - -
TQ1A TK1A OP4A TQ2A TK2A TQ3A TMRA - - - TI1A - - -
TAQ1 TAI2
TPSAB TAQ2 TAI3 - T4HAB TAQ3 TAK0 - - TAPU0 -
SNZAD T4R4L - -
TI2A TFR0A TSIAB -
TABSI SNZSI TABAD - - - - - - - - -
TFR1ATADAB TALA TAK1 - TAL1 TAK2 - - -
TL1A TI3A TFR2A
CMCK TPAA CRCK - - - - -
TL2A TK0A TFR3ATR3AB TAW1 - TLCA TW1A TW2A - - - - - TPU0A TPU1A - - - - TAW2 TAW3
RCP DWDT SCP - - - SST ADST
TAW4 TAPU1 -
TR1AB TAW5
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the loworder 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011
BL BML BLA BMLA SEA SZD
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VI VI VO VO VO Pd Topr Tstg Parameter Conditions Supply voltage Input voltage P0, P1, P2, P3, P4, D0-D7, RESET, XIN, XCIN, VDCE Input voltage SCK, SIN, CNTR0, CNTR1, INT0, INT1 Input voltage AIN0-AIN7 Output voltage Output transistors in cut-off state P0, P1, P2, P3, P4, D0-D9, RESET, SCK, SOUT, CNTR0, CNTR1 Output voltage C, XOUT, XCOUT Output voltage SEG0-SEG19, COM0-COM3 Power dissipation Ta = 25 C Operating temperature range Storage temperature range Ratings -0.3 to 6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 300 -20 to 85 -40 to 125 Unit V V V V V V V mW C C
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4524 Group
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = -20 C to 85 C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol VDD Parameter Supply voltage (when ceramic resonator is used) Conditions Mask ROM version f(STCK) 6 MHz f(STCK) 4.4 MHz f(STCK) 2.2 MHz One Time PROM version f(STCK) 6 MHz f(STCK) 4.4 MHz f(STCK) 2.2 MHz VDD VRAM VSS VLC3 VIH VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOH(peak) IOH(avg) IOH(avg) IOL(peak) IOL(peak) IOL(peak) IOL(avg) IOL(avg) IOL(avg) IOH(avg) IOL(avg) Supply voltage (when RC oscillation is used) RAM back-up voltage Supply voltage LCD power supply (Note 1) "H" level input voltage "H" level input voltage "H" level input voltage "H" level input voltage "L" level input voltage "L" level input voltage "L" level input voltage "L" level input voltage "H" level peak output current "H" level peak output current "H" level average output current (Note 2) "H" level average output current (Note 2) "L" level peak output current "L" level peak output current "L" level peak output current "L" level average output current (Note 2) "L" level average output current (Note 2) "L" level average output current (Note 2) "H" level total average current "L" level total average current P0, P1, D0-D6, SCK, SOUT P4, D7, C, CNTR0, CNTR1 P0, P1, D0-D6, SCK, SOUT P2, P3, P4, D7-D9, C, RESET, CNTR0, CNTR1
Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)*VLC3 At 1/3 bias: VLC1 = (1/3)*VLC3, VLC2 = (2/3)*VLC3 2: The average output current is the average value during 100 ms.
Limits Min. 4 2.7 2 4 2.7 2.5 2.7 1.8 0 2 2.5 0.8VDD 0.7VDD 0.85VDD 0.8VDD 0 0 0 0 VDD VDD VDD VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 0.15VDD -20 -10 -30 -15 -10 -5 -20 -10 24 12 24 12 10 4 12 6 15 7 5 2 -60 -60 80 80 Typ. Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Unit V
f(STCK) 4.4 MHz at RAM back-up mode Mask ROM version One Time PROM version P0, P1, P2, P3, P4, D0-D7, VDCE XIN, XCIN
RESET
V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA
SCK, SIN, CNTR0, CNTR1, INT0, INT1 P0, P1, P2, P3, P4, D0-D7, VDCE XIN, XCIN
RESET
SCK, SIN, CNTR0, CNTR1, INT0, INT1 VDD = 5 V P0, P1, P4, D0-D6 SCK, SOUT D7, C CNTR0, CNTR1 P0, P1, P4, D0-D6 SCK, SOUT D7, C CNTR0, CNTR1 P0, P1, P4 D0-D9, C, SCK, SOUT, CNTR0, CNTR1 P2, P3, RESET P0, P1, P4 D0-D9, C, SCK, SOUT, CNTR0, CNTR1 P2, P3, RESET VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V
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4524 Group
RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version: Ta = -20 C to 85 C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) Mask ROM version Conditions Through mode VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V Frequency/4, 8 mode VDD = 2 to 5.5 V One Time PROM Through mode version VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/4, 8 mode VDD = 2.5 to 5.5 V f(XIN) f(XIN) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic resonator selected, external clock input) VDD = 2.7 to 5.5 V Mask ROM version Through mode VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V Frequency/4, 8 mode VDD = 2 to 5.5 V One Time PROM Through mode version VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/4, 8 mode VDD = 2.5 to 5.5 V f(XCIN) Oscillation frequency (sub-clock) f(CNTR) Timer external input frequency tw(CNTR) Timer external input period ("H" and "L" pulse width) f(SCK) Serial I/O external input frequency tw(SCK) Serial I/O external input frequency ("H" and "L" pulse width) Power-on reset circuit valid supply voltage rising time SCK SCK Mask ROM version One Time PROM version VDD = 0 2 V VDD = 0 2.5 V 3/f(STCK) f(STCK)/6 Hz s 100 100 s Quartz-crystal oscillator CNTR0, CNTR1 CNTR0, CNTR1 3/f(STCK) Limits Min. Typ. Max. 6 4.4 2.2 6 4.4 6 6 4.4 2.2 6 4.4 6 4.4 4.8 3.2 1.6 4.8 3.2 4.8 4.8 3.2 1.6 4.8 3.2 4.8 50 kHz MHz MHz Unit MHz
f(STCK)/6 Hz s
TPON
Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
When ceramic resonator is used.
f(STCK) [MHz] 6
When RC oscillation is used.
f(STCK) [MHz]
When external clock is used.
f(STCK) [MHz]
4.8 4.4 4.4 3.2
2.2
Recommended operating condition
Recommended operating condition
1.6
Recommended operating condition
2 (2.5)
2.7
4
5.5
VDD [V]
2.7
5.5
VDD [V]
2 (2.5)
2.7
4
5.5
VDD [V]
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4524 Group
ELECTRICAL CHARACTERISTICS 1
(Mask ROM version: Ta = -20 C to 85 C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol VOH Parameter "H" level output voltage P0, P1, P4, D0-D6, SCK, SOUT VDD = 3 V VOH "H" level output voltage D7, C, CNTR0, CNTR1 VDD = 3 V VOL "L" level output voltage P0, P1, P4 VDD = 3 V VOL "L" level output voltage D0-D9, C, SCK, SOUT, CNTR0, CNTR1 VDD = 3 V VOL "L" level output voltage P2, P3, RESET VDD = 3 V IIH "H" level input current P0, P1, P2, P3, P4, D0-D7, VDCE, RESET, CNTR0, CNTR1, INT0, INT1 IIL "L" level input current P0, P1, P2, P3, P4, D0-D7, VDCE, SCK, SIN, CNTR0, CNTR1, INT0, INT1 VI = 0 V P0, P1 No pull-up -1 VI = VDD VDD = 5 V VDD = 5 V VDD = 5 V VDD = 5 V VDD = 5 V Test conditions IOH = -10 mA IOH = -3 mA IOH = -5 mA IOH = -1 mA IOH = -20 mA IOH = -6 mA IOH = -10 mA IOH = -3 mA IOL = 12 mA IOL = 4 mA IOL = 6 mA IOL = 2 mA IOL = 15 mA IOL = 5 mA IOL = 9 mA IOL = 3 mA IOL = 5 mA IOL = 1 mA IOL = 2 mA Limits Min. 3 4.1 2.1 2.4 3 4.1 2.1 2.4 2 0.9 0.9 0.6 2 0.9 1.4 0.9 2 0.6 0.9 1 V V V V Typ. Max. Unit V
A
A
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4524 Group
ELECTRICAL CHARACTERISTICS 2
(Mask ROM version: Ta = -20 C to 85 C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol IDD Parameter Supply current at active mode VDD = 5 V Test conditions f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) VDD = 5 V f(XIN) = 4 MHz f(XCIN) = 32 kHz VDD = 3 V f(XIN) = 4 MHz f(XCIN) = 32 kHz at active mode (with a quartz-crystal oscillator) VDD = 5 V f(XIN) = stop f(XCIN) = 32 kHz VDD = 3 V f(XIN) = stop f(XCIN) = 32 kHz at clock operation mode (POF instruction execution) at RAM back-up mode (POF2 instruction execution) RPU Pull-up resistor value Ta = 25 C VDD = 5 V VDD = 3 V VI = 0 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V f(RING) f(XIN) On-chip oscillator clock frequency Frequency error (with RC oscillation, error of external R, C not included ) (Note) RCOM RSEG RVLC COM output impedance SEG output impedance Internal resistor for LCD power supply VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V When dividing resistor 2r 3 selected When dividing resistor 2r 2 selected When dividing resistor r 3 selected When dividing resistor r 2 selected
Note: When RC oscillation is used, use the external 33 pF capacitor (C).
Limits Min. Typ. 1.4 1.6 2 2.8 1.1 1.2 1.5 2 0.4 0.5 0.6 0.8 55 60 65 70 12 13 14 15 20 5 0.1 Max. 2.8 3.2 4 5.6 2.2 2.4 3 4 0.8 1 1.2 1.6 110 120 130 140 24 26 28 30 60 15 1 10 6
Unit mA
(with a ceramic resonator) f(XIN) = 6 MHz f(XCIN) = 32 kHz
f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) VDD = 5 V VDD = 3 V
mA
mA
A
A
f(XCIN) = 32 kHz
A A
VDD = 5 V VDD = 3 V
30 50
60 120 0.2 0.2 1 0.4
P0, P1, RESET VT+ - VT- Hysteresis SCK, SIN, CNTR0, CNTR1, INT0, INT1 VT+ - VT- Hysteresis RESET
125 250
k V V
VDD = 5 V VDD = 3 V VDD = 5 V 10 %, Ta = 25 C VDD = 5 V 10 %, Ta = 25 C
1 0.5
2 1
3 1.8 17 17
MHz %
1.5 2 1.5 2 300 200 150 100 480 320 240 160
7.5 10 7.5 10 960 640 480 320
k k k
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4524 Group
A/D CONVERTER RECOMMENDED OPERATING CONDITIONS
(Comparator mode selected, Ta = -20 C to 85 C, unless otherwise noted) Symbol VDD VIA f(XIN) Parameter Supply voltage Analog input voltage Oscillation frequency VDD = 2.7 to 5.5 V f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) Ta = 25 C Ta = -20 to 85 C Conditions Min. 2.7 3 0 0.8 0.4 0.2 0.1 Limits Typ. Max. 5.5 5.5 VDD V MHz Unit V
A/D CONVERTER CHARACTERISTICS
(Ta = -20 C to 85 C, unless otherwise noted) Symbol - - - V0T VFST IADD TCONV Parameter Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage A/D operating current (Note 1) A/D conversion time Ta = 25 C, VDD = 2.7 V to 5.5 V Ta = -20 C to 85 C, VDD = 3 V to 5.5 V Ta = 25 C, VDD = 2.7 V to 5.5 V Ta = -20 C to 85 C, VDD = 3 V to 5.5 V VDD = 5.12 V VDD = 3.072 V VDD = 5.12 V VDD = 3.072 V VDD = 5 V VDD = 3 V f(XIN) = 6 MHz f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) - - - Comparator resolution Comparator error (Note 2) Comparator comparison time VDD = 5.12 V VDD = 3.072 V f(XIN) = 6 MHz f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) 0 0 5110 3063 10 6 5120 3069 0.3 0.1 20 12 5130 3075 0.9 0.3 248 124 62 31 8 20 15 32 16 8 4 mV mV mA 0.9 LSB Test conditions Min. Limits Typ. Max. 10 2 Unit bits LSB
s
bits mV
s
Notes 1: When the A/D converter is used, IADD is added to IDD (supply current). 2: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref Vref = VDD 256 n
n = Value of register AD (n = 0 to 255)
Rev.2.00 Jul 27, 2004 REJ03B0091-0200Z
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4524 Group
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = -20 C to 85 C, unless otherwise noted) Symbol VRST IRST TRST Parameter Detection voltage (Note 1) Operation current Detection time Ta = 25 C at power down (Note 2) VDD (VRST-0.1 V) (Note 3) VDD = 5 V VDD = 3 V Test conditions Min. 3.3 2.7 Limits Typ. 3.5 50 30 0.2 Max. 3.7 4.2 100 60 1.2 Unit V
A
ms
Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. 2: After the SVDE instruction is executed, the voltage drop detection circuit is valid at power down mode. 3: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST-0.1 V].
BASIC TIMING DIAGRAM
Machine cycle
Parameter
Mi
Mi+1
Pin (signal) name
System clock
STCK
Port D output
D0-D9
Port D input
D0-D7
Ports P0, P1, P2, P3, P00-P03 P10-P13 P4 output P20-P23 P30-P33 P40-P43 Ports P0, P1, P2, P3, P00-P03 P10-P13 P4 input P20-P23 P30-P33 P40-P43 Interrupt input INT0, INT1
Rev.2.00 Jul 27, 2004 REJ03B0091-0200Z
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4524 Group
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4524 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 25 shows the product of built-in PROM version. Figure 75 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. Table 25 Product of built-in PROM version PROM size Part number ( 10 bits) M34524EDFP 16384 words
RAM size ( 4 bits) 512 words
Package 64P6N-A
ROM type One Time PROM [shipped in blank]
PIN CONFIGURATION (TOP VIEW)
COM0 COM1 COM2 COM3 P00 P01 P02 P03 P10 P11 P12 P13 D0 D1
D2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VLC3/SEG0 VLC2/ SEG1 VLC1/SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D4/SIN D5/SOUT D6/SCK CNVSS VDCE
M34524EDFP
XCIN XCOUT
VDD VSS XOUT XIN
RESET D7/CNTR0 C/ CNTR1
D8/INT0 D9/I NT1
P33/ AIN7 P32/ AIN6 P31/ AIN5 P30/ AIN4 P23/ AIN3
Outline 64P6N-A
Fig. 75 Pin configuration of built-in PROM version
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P22/ AIN2
P21/ AIN1
P20/ AIN0
SEG17 SEG18 SEG19 P43 P42
SEG16
P41 P40
4524 Group
(1) PROM mode
The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapter is listed in Table 26. Contact addresses at the end of this data sheet for the appropriate PROM programmer. * Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 76.
Table 26 Programming adapter Part number Name of Programming Adapter M34524EDFP PCA7448
Address 000016
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
(2) Notes on handling
A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. For the One Time PROM version shipped in blank, Renesas Technology corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 77 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped).
3FFF16 400016
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
7FFF16
Fig. 76 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 C exceeding 100 hours.
Fig. 77 Flow of writing and test of the product shipped in blank
Rev.2.00 Jul 27, 2004 REJ03B0091-0200Z
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4524 Group
PACKAGE OUTLINE
64P6N-A
EIAJ Package Code QFP64-P-1414-0.80 HD D JEDEC Code -- Weight(g) 1.11 Lead Material Alloy 42
Plastic 64pin 1414mm body QFP
MD
e
1
48
b2
64
49
I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Min Nom Max 3.05 -- -- 0 0.1 0.2 2.8 -- -- 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 0.8 -- -- 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 -- -- 0.1 -- -- 0 10 -- 0.5 -- -- -- -- 1.3 14.6 -- -- -- -- 14.6
16
33
HE
E
17
32
A
L1
A2
F
A1
e y
b
L Detail F
Rev.2.00 Jul 27, 2004 REJ03B0091-0200Z
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c
ME
REVISION HISTORY
Rev. Date Page 1.00 Oct. 11, 2001 1.10 Nov. 07, 2001 - 6 22 40 57 61 69
4524 Group Data Sheet
Description Summary
First edition issued Note; f(RING) f(RING)/8 Table 4; (th second) External 0 interrupt External 1 interrupt (13); * Prescaler; reload register RPS prescaler data (2); timer 2 count source selection bit timer LC count source selection bit (5); * Internal dividing registor; by setting bit 2 of register L1 to "0" Fig. 53; Stabilizing time e ; high low, Note 1; power down clock operating Prescaler ; reload register RPS prescaler data 75 TAK0, TK0A, TAK1, TK1A, TAK2, TK2A instructions revised 90 RBK; Flag CY; "0" "-" 102 SBK (Reset Bank Flag) SBK (Set Bank Flag) 104 TAB; Grouping; Other operations Register to register transfer 111 TAL1 (Transfer data to Accumulator from register LA) 116 TAL1 (Transfer data to Accumulator from register L1) TAK0, TK0A, TAK1, TK1A, TAK2, TK2A instructions revised 145 WRST, DWDT instructions revised 147 2.00 Jul. 27, 2004 All pages Words standardized: On-chip oscillator, A/D converter Power dissipation revised. 4 ____________ Description of RESET pin revised. 5 Table 6: Notes added. 24 Fig.26 : Note 9 added. 34 Some description revised. 44 Fig.31: "DI" instruction added. 45 Table 11:Revised. 46 (5) LCD power supply circuit revised. 61 Fig.51: State of quartz-crystal oscillator added. 65 VOLTAGE DROP DETECTION CIRCUIT revised. 66 Table 21: Port level revised and Note 7 added. 67 Fig.55: 69 * Note 5 added, * "T5F" added to the transitions between from state E to states B, A, C and D * "Key-on wakeup""Wakeup" Note on Voltage drop detection circuit added. 78 Note on Difference between Mask ROM version and One Time PROM version added. Note on Power Source Voltage added. Condition of IOL(peak) and IOL(avg) revised. 151
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c)2001, 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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